Which PSL is included in the VHDL-200X LRM sent to IEEE for

R

Reuven

Guest
Hi all,

Thankfully, PSL is included in the new VHDL LRM. However, which
"version" of PSL will be used,

Accellera 1.1
IEEE- 1850
something else ???

thanks
 
"Reuven" <rpaley000@gmail.com> wrote in message
news:1186004641.940808.86660@i38g2000prf.googlegroups.com...
Hi all,

Thankfully, PSL is included in the new VHDL LRM. However, which
"version" of PSL will be used,

Accellera 1.1
IEEE- 1850
something else ???

thanks
Click to expand...
From the Draft IEEE P1076/D3.0 June 20, 2006 VHDL Language Reference manual:

0.2.4 Incorporation of PSL
VHDL incorporates the simple subset of the Property Specification Language
(PSL) as an embedded language for
formal specification of the behavior of a VHDL description. PSL is defined
by IEEE 1850-2005 [B32]. All PSL
constructs that appear in a VHDL description must conform to the VHDL flavor
of PSL. Within this standard,
reference is made to syntactic rules of PSL. Each such reference has the
italicized prefix PSL_ and corresponds to the
syntax rule in IEEE 1850-2005 with the same name but without the prefix.

Regards,
Hans.
www.ht-lab.com
 
Thank you Hans,

Your reply was quick and informative. Now, i'm more eager to start
using 1076-2006 after it's approved and implemented in a Modelsim.

r
 
On 2 Aug., 02:22, Reuven <rpaley...@gmail.com> wrote:
Your reply was quick and informative. Now, i'm more eager to start
using 1076-2006 after it's approved and implemented in a Modelsim.
Click to expand...
Talking about VHDL 1076-2006, will there be a way to declare something
like

type signed_vector is array(integer range <>) of signed;

? I am just doing some DSP work and just tried to implement

function quantize(samples : real; bitwidth : positive) return
signed_vector;
function dequantize(quantized : signed_array) return real_vector;

I can't find a way to do this with VHDL'93. Suggestions?

Thanks, Torsten
 
In news:1186042327.649752.67240@w3g2000hsg.googlegroups.com
timestamped Thu, 02 Aug 2007 01:12:07 -0700, Torsten
Landschoff <t.landschoff@gmx.de> posted:
|----------------------------------------------------------------------|
|"On 2 Aug., 02:22, Reuven <rpaley...@gmail.com> wrote: |
|> Your reply was quick and informative. Now, i'm more eager to start |
|> using 1076-2006 after it's approved and implemented in a Modelsim. |
| |
|Talking about VHDL 1076-2006, will there be a way to declare something|
|like |
| |
|type signed_vector is array(integer range <>) of signed; |
| |
|? I am just doing some DSP work and just tried to implement |
| |
|function quantize(samples : real; bitwidth : positive) return |
|signed_vector; |
|function dequantize(quantized : signed_array) return real_vector; |
| |
|I can't find a way to do this with VHDL'93. Suggestions? |
| |
|Thanks, Torsten" |
|----------------------------------------------------------------------|

It is not entirely clear to me what you are trying to do here. Do you
want quantize overloaded by several functions, each of which will
return a signed_vector of a different length according to bitwidth?

VHDL2007 will include

package fixed_generic_pkg is
generic (fixed_round_style: BOOLEAN;
fixed_overflow_style: BOOLEAN;
fixed_guard_bits: NATURAL;
no_warning: BOOLEAN);
type ufixed is array (INTEGER range <>) of STD_ULOGIC;
type sfixed is array (INTEGER range <>) of STD_ULOGIC;
....
end package fixed_generic_pkg;

but this would not involve overloading because each instantiation of
fixed_generic_pkg would need a different name. VHDL2007 does not have
generic instantiations in which the parameter is a type (Ada has these
kinds of generics but I do not know whether the Ada synthesis tools
are very good nor whether this is supported by any of them, and I read
a paper by one of their developers who claimed that VHDL is better),
and these still would not allow overloading.

VHDL2007 apparently will have object orientation but I do not know
much about VHDL2007's OO.

In VHDL93, perhaps you could be satisfied with preprocessing in
another language and producing VHDL source code as output; or
inefficiently but simply using the longest array length you could need
and simply ignoring the irrelevant bits as indicated by bitwidth; or
type signed_vector is array(integer range <>) of signed;

type pointed_to_type is
record
the_array : signed_vector;
end record;

type access_type is access pointed_to_type;

function quantize(samples : real; bitwidth : positive) return
access_type;

and constrain the length of the_array in an instance of
pointed_to_type when running quantize.

Perhaps better ways exist.

Regards,
Colin Paul Gloster
 
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