Which package to use?

H

Hendra Gunawan

Guest
Hi folks,
I consider myself as very good in Verilog. But I got lost with all the data
types, packages and libraries in VHDL.
How do I know when to declare inputs/outputs or signals as std_logic,
unsigned, signed, integer, bits, etc?
How do I know when to use library IEEE.STD_LOGIC_1164, UNSIGNED, SIGNED,
ARITHMETIC, NUMERIC etc?
Surely I can look inside the library text file, but there are bunch of
functions there that doesn't give enough explanations of what it supposed to
do!
Thanks in advance!

Hendra
 
Hendra Gunawan wrote:

How do I know when to declare inputs/outputs or signals as std_logic,
unsigned, signed, integer, bits, etc?
Click to expand...
Take std_logic / std_logic_vector or std_ulogic / std_ulogic_vector.

Often synthesis tools are configured to convert any input/output signal
to one of these types (often std_Ulogic(_vector) is chosen).


How do I know when to use library IEEE.STD_LOGIC_1164, UNSIGNED, SIGNED,
ARITHMETIC, NUMERIC etc?
Click to expand...
IEEE.STD_LOGIC_1164 and IEEE.numeric_std are recommended. The other
mentioned libraries are implemented different on different simulators
and synthesis tools - although it seems, that they have been
standardisized by IEEE.

So you may have problems when using one of these not standardisized
libraries with the behavior of the simulator and the synthesis tool,
because both could have a different implementation of these libraries.


Numeric_std is a "new" library. Some older tools (really old ;-)) may
not provide it.


Ralf
 
Hendra,
My recommendation:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;

For ports use types: std_logic and std_logic_vector
This will make your design flow most portable.

For inside your design, use types:
std_logic, std_logic_vector, unsigned, and signed

For all math operations use types: unsigned and signed

You will need to know how to get between types:
std_logic_vector, unsigned, signed, and integer

A tutorial on this is at:
http://www.synthworks.com/papers
see the paper titled: VHDL Math Tricks of the Trade


From time to time, I will also use the package,
std_logic_unsigned. This package is not an IEEE package.
I expect it to be replaced with an IEEE standard version
that will perhaps be named numeric_unsigned.
This package allows you to do unsigned math with
std_logic_vector. Beware: some think this is bad, some think
this is good. I think it is only ok in the following
contexts: counters and testbench algorithmic manipulation
of std_logic_vector objects. I also highly discourage the
use of the package std_logic_signed and do not expect to
see a standard version of this package.

The VHDL-200X project will be improving the packages some,
however, this is what we have for the short term
(additions like unary reduction and others).

Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Hendra Gunawan wrote:
Hi folks,
I consider myself as very good in Verilog. But I got lost with all the data
types, packages and libraries in VHDL.
How do I know when to declare inputs/outputs or signals as std_logic,
unsigned, signed, integer, bits, etc?
How do I know when to use library IEEE.STD_LOGIC_1164, UNSIGNED, SIGNED,
ARITHMETIC, NUMERIC etc?
Surely I can look inside the library text file, but there are bunch of
functions there that doesn't give enough explanations of what it supposed to
do!
Thanks in advance!

Hendra
Click to expand...
 
From time to time, I will also use the package,
std_logic_unsigned. This package is not an IEEE package.
Click to expand...
If I write my code like this:

library IEEE;
use std_logic_unsigned.all;

Does it still means that unsigned is still not IEEE standard? I thought that
if we use the clause "library IEEE", then any libray after the "use" clause
will refer to IEEE library. And IEEE is always standard. Am I missing
something here?

Hendra
 
On Tue, 27 Apr 2004 21:43:24 -0700, "Hendra Gunawan"
<u1000393@email.sjsu.edu> wrote:

If I write my code like this:
library IEEE;
use std_logic_unsigned.all;
Does it still means that unsigned is still not IEEE standard?
Click to expand...
Indeed. Fortunately, DASC have sufficiently good taste
to refuse to standardise it :)

I thought that
if we use the clause "library IEEE", then any libray after the "use" clause
will refer to IEEE library. And IEEE is always standard. Am I missing
something here?
Click to expand...
No. It's an historical accident, and you have every reason
to be a little confused.

Back in the Bad Old Days when there was no IEEE numeric standard
package, lots of vendors (most notably Synopsys) did their own
thing. Many of these vendor packages were put into
"library IEEE" for user convenience, and that's where they've
stayed - remember to sing the EDA industry anthem every
morning...
WE MUST NOT BREAK LEGACY CODE
(repeated many times)
EVEN IF IT LEAVES US IN A MESS

There was some suggestion that IEEE should create a small
"administrative" standard that would define exactly what should
and should not go into "library IEEE". I'm not sure exactly
where that effort got to - maybe Jim Lewis can give us an
executive summary.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
Jonathan Bromley wrote:


Back in the Bad Old Days when there was no IEEE numeric standard
package, lots of vendors (most notably Synopsys) did their own
thing. Many of these vendor packages were put into
"library IEEE" for user convenience, and that's where they've
stayed - remember to sing the EDA industry anthem every
morning...
WE MUST NOT BREAK LEGACY CODE
(repeated many times)
EVEN IF IT LEAVES US IN A MESS

There was some suggestion that IEEE should create a small
"administrative" standard that would define exactly what should
and should not go into "library IEEE". I'm not sure exactly
where that effort got to - maybe Jim Lewis can give us an
executive summary.
Click to expand...
The "library IEEE" standard was disolved into the VHDL-200X
effort, however, as Jonathan mentioned, it takes the perspective
that only IEEE standards shall be put in there (therefor
don't do it again), however, it wisely does not direct the
current non-standard packages to be removed. Otherwise some
people would be obliged to do needless edits to historical
code.

Cheers,
Jim


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Hendra Gunawan wrote:

From time to time, I will also use the package,
std_logic_unsigned. This package is not an IEEE package.


If I write my code like this:

library IEEE;
use std_logic_unsigned.all;

Does it still means that unsigned is still not IEEE standard?
Click to expand...
This is slightly ambiguous, I am taking by "unsigned" that you
mean the package "std_logic_unsigned" as you referred to above.
Std_logic_unsigned is from Synopsys. Its purpose is to allow
you to do unsigned math with the type std_logic_vector (and
has nothing to do with the type unsigned which is defined
in the IEEE standard package numeric_std).

Like Jonathan said, std_logic_unsigned is not an IEEE standard,
however do note it is well supported by most EDA tools and going
further, the 1076.3 working group does plan to have a
numeric_std like flavor of a package like this named either
numeric_unsigned/numeric_std_unsigned.

You will note that some consider the use of a package like
std_logic_unsigned/numeric_unsigned to be a bad practice.
They feel that for math you should be using the types
unsigned and signed. I am partially in this camp. I believe
that it is ok to use std_logic_unsigned for counters (which
I don't really consider unsigned or signed) and for
testbenches (where I may be applying an algorithm to an
address bus - which really isn't numeric).


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
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