Which is the most beautiful and memorable hardware structure

[Weng Tianxiang]

Hi,
From the first moment I learn how stack segment and stack pointer are
used to link all subroutines in PC, I have been appreciating the
hardware structure as I can and I think it is the the most beautiful
and memorable hardware structure I have learn from the CPU structure.

I want to know who invented the structure. Is an IBM engineer?

And it is strange enough that after PC was created, no big new
structure in CPU has ever invented. MESI protocol? No. Changing 1 core
to 2 core, or even 8 cores is considered as a big invention? No.

Oh, I forgot to mention the most important invention since then is the
Mouse we use it every day.

Any idea?

Weng

 

[whygee]

Sandro wrote:

A little bit OT...
Yes, this thread would better suit the comp.arch group.

There are great CPU architecture specialists there

Regards
Sandro
yg

--
http://ygdes.com / http://yasep.org

 

[Sandro]

On Mar 29, 4:06 am, Weng Tianxiang <wtx...@gmail.com> wrote:

...
From the first moment I learn how stack segment and stack pointer are
used to link all subroutines in PC, I have been appreciating the
hardware structure as I can and I think it is the the most beautiful
and memorable hardware structure I have learn from the CPU structure.
I want to know who invented the structure. Is an IBM engineer?
And it is strange enough that after PC was created, no big new
structure in CPU has ever invented. MESI protocol? No. Changing 1 core
to 2 core, or even 8 cores is considered as a big invention? No.
Oh, I forgot to mention the most important invention since then is the
Mouse we use it every day.
Any idea?
...
Weng

A little bit OT... anyway I think you mean the "von Neumann
architecture" and
the "Harvard architecture" both being maybe the most (but not the
only)
used CPU architectures.
You can use as start point the followings:
http://en.wikipedia.org/wiki/Von_Neumann_architecture
http://en.wikipedia.org/wiki/Harvard_architecture

Regards
Sandro

 

[jacko]

I think it was a high level language feature first.

Are you talking of indexed indirect addressing mode (reg+#immediate)
or the link unlink instruction sets for setting the stack pointer?
Would the 6502 8 bit micro (ZZ),Y mode count? Or are you more PDP-11?

 

[Jonathan Bromley]

On Sun, 28 Mar 2010 19:06:23 -0700 (PDT), Weng Tianxiang wrote:

From the first moment I learn how stack segment and stack pointer are
used to link all subroutines in PC, I have been appreciating the
hardware structure as I can and I think it is the the most beautiful
and memorable hardware structure I have learn from the CPU structure.

Aw, c'mon. Most of that is software - the only hardware
requirements are the ability to copy a stack pointer
to/from some other place, and the ability to construct an
address that's offset from a register or memory value.

For sheer luminous beauty, let's hear it for the PDP-8's
JMS instruction...

oh, maybe not. OK, second attempt. SPARC register windows.

No? Don't like that? OK, the Transputer's tiny 3-register
evaluation stack, with context switches permitted only at
points where the stack is known to be empty. The
21st century operating system wonks could REALLY learn
something about lightweight elegance from that one.

What about the whole idea of a stack? How cool is that,
if you haven't seen it before?

Set-associative cache?

Sheesh, the field is so crowded with beautiful, genius-level
ideas - but we're all so familiar with them that we don't
see how hard it must have been to come up with them in
the first place. Trying to single out just one is silly.

Oh, I forgot to mention the most important invention since then is the
Mouse we use it every day.

Crap.

Are you *really* trying to convince us that the mouse is
more important, elegant, beautiful than...
- convolution codes? and Shannon's theorem?
- quadrature modulation?
- Boolean algebra? Set theory?
- The Fourier transform?
- crystallography?
- The Goldberg Variations?

The kind of slavish technology-worship that your original
question exemplifies is depressing and backward-looking;
it leads us into relying on past achievements instead of
being thrilled by what might be if only we keep questioning.
It's the kind of thinking that should (but too often does
not) give technologists and businessmen a bad reputation.

We technologists are the 21st-century equivalent of the
19th century ironfounders. We're exploiting the heroic
achievements of the recent past to build the infrastructure
that the future needs. We are facilitators, not visionaries.
The next half-century belongs to the molecular biologists
and geneticists, and we are merely there to help out with
the menial work. Get a sense of proportion.
--
Jonathan Bromley

 

[whygee]

Jonathan Bromley wrote:

Crap.

Are you *really* trying to convince us that the mouse is
more important, elegant, beautiful than...
- convolution codes? and Shannon's theorem?
- quadrature modulation?
- Boolean algebra? Set theory?
- The Fourier transform?
- crystallography?
- The Goldberg Variations?

I'll add the Burrows-Wheeler transform which enables great compression
and the Reed-Solomon method for forward error correction, used in so many places.
I wish I could come up with something as mind-boggling AND useful.

The kind of slavish technology-worship that your original
question exemplifies is depressing and backward-looking;
it leads us into relying on past achievements instead of
being thrilled by what might be if only we keep questioning.
It's the kind of thinking that should (but too often does
not) give technologists and businessmen a bad reputation.
he seems to be too young or too noob to understand that yet.

Give him 10 or 20 years...

Get a sense of proportion.
This comes with learning, and Internet is a great facilitator

for this. And other less noble things, but so is the human nature...

yg
--
http://ygdes.com / http://yasep.org

 

[MitchAlsup]

The most memorable hardware structure is the vector indirect
addressing mode.

Mitch

 

[Andrew Reilly]

On Mon, 29 Mar 2010 19:39:12 -0700, MitchAlsup wrote:

The most memorable hardware structure is the vector indirect addressing
mode.

I had a soft spot for the 3D-matrix-stride post-modify addressing mode
that the Motorola 56000 had, for a while. (The processor still has the
mode, I'm no longer so sure it was a good idea...) Certainly memorable.

Cheers,

--
Andrew

 

In article <27ebdb37-e3ba-4559-be7d-d7f3b6613d77@30g2000yqi.googlegroups.com>,
MitchAlsup <MitchAlsup@aol.com> wrote:

The most memorable hardware structure is the vector indirect
addressing mode.

Yes. There were and are more bizarre ones, but they are Not Memorable
(see Sellars and Yeatman).


Regards,
Nick Maclaren.

 

[Jonathan Bromley]

On Mar 30, 10:38 am, n...@cam.ac.uk wrote:

Yes.  There were and are more bizarre ones, but they are Not Memorable
(see Sellars and Yeatman).

Ooooh, I like that. Always good to bring a bit of high culture
into the discussion.

It may be Memorable, hut was it a Good Thing?

_Sellar_ and Yeatman, I think you'll find (without the trailing 's').

Thanks for tickling a long-dormant and much cherished memory.
--
Jonathan Bromley

 

[Jason Zheng]

On Sun, 28 Mar 2010 19:06:23 -0700 (PDT)
Weng Tianxiang <wtxwtx@gmail.com> wrote:

<snip>

And it is strange enough that after PC was created, no big new
structure in CPU has ever invented. MESI protocol? No. Changing 1 core
to 2 core, or even 8 cores is considered as a big invention? No.

My favorite is the Translation Look-aside Buffers (TLB), of course
invented by the IBM engineers. You have to appreciate the way it sounds
(and its irrelevance to its true purpose).

 

[Tim McCaffrey]

In article <hosgq9$h5m$1@smaug.linux.pwf.cam.ac.uk>, nmm1@cam.ac.uk says...

In article
27ebdb37-e3ba-4559-be7d-d7f3b6613d77@30g2000yqi.googlegroups.com>,
MitchAlsup <MitchAlsup@aol.com> wrote:
The most memorable hardware structure is the vector indirect
addressing mode.

Yes. There were and are more bizarre ones, but they are Not Memorable
(see Sellars and Yeatman).


Regards,
Nick Maclaren.

I'll see your vector indirect mode, and add segment descriptors!

(Really, is anything more compilcated than VALC?)
(Unisys Clearpath Libra (MCP) systems)
(aka. A series)

- Tim

 

[Weng Tianxiang]

On Mar 30, 10:41 am, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:

On Sun, 28 Mar 2010 19:06:23 -0700 (PDT)

Weng Tianxiang <wtx...@gmail.com> wrote:

snip

And it is strange enough that after PC was created, no big new
structure in CPU has ever invented. MESI protocol? No. Changing 1 core
to 2 core, or even 8 cores is considered as a big invention? No.

My favorite is the Translation Look-aside Buffers (TLB), of course
invented by the IBM engineers. You have to appreciate the way it sounds
(and its irrelevance to its true purpose).

Haha, some people don't appreciate stack segment and stack pointer.

There two reasons I appreciate most:
1. It is very simple;
2. I handles all subroutine calls with prefect beauty for last 60
years.

3 years ago when I first read BW transform, I was in awe in such a way
that made me to excitement for a week.

But sadly I found that BW transform cannot get the high compression
rate even though we don't pay attention on the time the transform
needs.

I joined compression group and found there were few discussions on the
BW transform, the main reason is its not highest compression rate.

Weng

 

[glen herrmannsfeldt]

In comp.arch.fpga Jason Zheng <Xin.Zheng@jpl.nasa.gov> wrote:
(snip)

My favorite is the Translation Look-aside Buffers (TLB), of course
invented by the IBM engineers. You have to appreciate the way it sounds
(and its irrelevance to its true purpose).

If you read the IBM description of virtual storage, you would
first believe that it went to the segment and page tables for
each reference. That would make everything three times slower,
so there is the TLB to speed thing up. Always interesting to
me is that the IBM name stuck, unlike many IBM names.
(Data set, IPL, to name two.)

The TLB is carefully documented by IBM, including the PTLB
instruction. (Purge TLB.) On the other hand, IBM doesn't
document much about the data and/or instruction cache, leaving
that up to the implementations to get right. Also, regarding
virtual storage, there is the STO (segment table origin) cache
that is also not documented by the architecture, but needed
to speed thing up in the case of multiple address spaces.

-- glen

 

[Rob Warnock]

MitchAlsup <MitchAlsup@aol.com> wrote:
+---------------
| The most memorable hardware structure is the vector indirect
| addressing mode.
+---------------

I was always rather fond of the PDP-10's multi-level indirect addressing
which allowed additional indexing with a different accumulator at each
level of indirection, and how that permitted multi-dimension array indexing
to be done in a *single* instruction, albeit requiring auxiliary Iliffe
vectors for the arrays [as was done in ALGOL-10]. Quoting myself:

Newsgroups: alt.folklore.computers
Date: Sun, 30 Aug 2009 06:03:04 -0500
From: rpw3@rpw3.org (Rob Warnock)
Subject: Re: PDP-10 Assembly Language Questions
Message-ID: <HrWdnRhVz531wQfXnZ2dnUVZ_v6dnZ2d@speakeasy.net>
...
For, say, a three-dimensional array, if A, B, & C were already
in the proper registers, then "FOO[A,B,C] := FOO[A,B,C] + 1"
could be done in *one* instruction!! (No joke!)
What, you don't believe me? ;-} Here's the code:

MOVE T1,A ; Load up the array indices
MOVE T2,B
MOVE T3,C
AOS @FOO(T1) ; Increment FOO[A,B,C] (and don't skip).

[Assumes the first level of Iliffe vectors has the indirect-addressing
bit on and "T2" in the index field, and the second level of Iliffe vectors
has the indirect-addressing bit *off* and "T3" in the index field.]


-Rob

-----
Rob Warnock <rpw3@rpw3.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607

 

[Andy \"Krazy\" Glew]

The two hardware datastructures supporting out of order execution:

Reservation stations.

And, less beautifully, the register renaming map.

But then I am biased.

--

Really, I do think that the reservation stations are beautiful. Even the naive CAM implementation. Especially since
there are more efficient implementations that are logically equivalent.

I am also pretty high on bit matrix schedulers.

 

[Andy \"Krazy\" Glew]

On 3/29/2010 7:39 PM, MitchAlsup wrote:

The most memorable hardware structure is the vector indirect
addressing mode.

Mitch

Aagh! No! Although work I did on that veered towards reservation stations, which I like.

Nvidia has shown that vector indirect is unnecessary on a SIMT.

Although^2, it turns out that very similar hardware is needed for SIMT scalar indirect.

 

[glen herrmannsfeldt]

In comp.arch.fpga "Andy \"Krazy\" Glew" <ag-news@patten-glew.net> wrote:

The two hardware datastructures supporting out of order execution:

Reservation stations.

And, less beautifully, the register renaming map.

Both from the IBM 360/91, as far as I know.

S/360 has only four floating point registers, so register
renaming was pretty important for out-of-order execution.

OK, how about imprecise interrupts?

-- glen

 

[James Harris]

On 29 Mar, 22:36, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

....

No?  Don't like that?  OK, the Transputer's tiny 3-register
evaluation stack, with context switches permitted only at
points where the stack is known to be empty.  The
21st century operating system wonks could REALLY learn
something about lightweight elegance from that one.

And from its one-byte instructions. Four-bit opcode and four-bit data
fields lead to 29 of the most-used instructions taking just one byte
and allowing for about 256 others to be encoded in two bytes (though
some used more). All this made effective on a 32-bit machine in the
1980s!

Of course the stack and zero-operand addressing made such tiny
encoding possible. These days a single stack would probably effect a
dependency between instructions which did not need one. Perhaps today
such would be built as many micro-cores.

James

 

In article <houi8s$rdm$1@naig.caltech.edu>,
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:

In comp.arch.fpga "Andy \"Krazy\" Glew" <ag-news@patten-glew.net> wrote:
The two hardware datastructures supporting out of order execution:

Reservation stations.

And, less beautifully, the register renaming map.

Both from the IBM 360/91, as far as I know.

S/360 has only four floating point registers, so register
renaming was pretty important for out-of-order execution.

OK, how about imprecise interrupts?

Not a problem, until you try to resume after trapping them

And the reason they were a problem was that they DID'T have a
lot of data structure to support them ....

I like them, as a design methodology, but only if integrated into
a restartable code sequence design and/or NOT used for anything
that might need resumption. E.g. one of the Alpha's most stupid
mistakes was to try and merge them with the use of interrupts for
supporting IEEE's edge cases. The 8087 was just plain idiotic.


Regards,
Nick Maclaren.