Which HVL is the most popular?

[Hendra Gunawan]

Hi folks,
I want to learn Hardware Verification Language (HVL). Which HVL is the most
popular for FPGA design?
I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron
books. Are there other Hardware Verification Languages?
Say I designed something in FPGA with Verilog or VHDL. How do I know that it
is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?

Hendra

 

[Jim Granville]

Hendra Gunawan wrote:

Hi folks,
I want to learn Hardware Verification Language (HVL). Which HVL is the most
popular for FPGA design?
I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron
books. Are there other Hardware Verification Languages?
Say I designed something in FPGA with Verilog or VHDL. How do I know that it
is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?

You could also look here :
http://research.microsoft.com/fse/asml/

-jg

 

[Jon Beniston]

"Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:<c4qr0p$6j7q9$1@hades.csu.net>...

Hi folks,
I want to learn Hardware Verification Language (HVL). Which HVL is the most
popular for FPGA design?
I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron
books. Are there other Hardware Verification Languages?
Say I designed something in FPGA with Verilog or VHDL. How do I know that it
is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?

Hendra

http://www.jeda.org/

Cheers,
JonB

 

[Jim Lewis]

Hendra,
Both VHDL (vhdl-200x) and Verilog (SystemVerilog) are being
extended to include HVL constructs. For education, either
e or Vera would be ok, but perhaps long term we can be back
at one language for all of the design (be it your choice of
VHDL or Verilog).

Cheers,
Jim

Hendra Gunawan wrote:

Hi folks,
I want to learn Hardware Verification Language (HVL). Which HVL is the most
popular for FPGA design?
I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron
books. Are there other Hardware Verification Languages?
Say I designed something in FPGA with Verilog or VHDL. How do I know that it
is time to verify my design with HVL as opposed to Verilog/VHDL testbenches?

Hendra

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~