which feature do i need to run MSPS?

[ponderboy]

After extracting pararistic elment such as R and C,I want to
backanotation pararistic elment to schematic and do pararisric post
simulation,but cdsdoc told me that i need a MSPS licnese to run,so
could anyone tell me which feature or licnesedo i need to run MSPS?

 

[Bernd Fischer]

I think no extra license feature is required to do that or it's included
in the DFII or Assura features.

But be aware you can not do a post layout simulation on
your schematic with backannotated parasitics, this feature
is just a viewing option, which gives the designer a idea where
the parasitic elements are located in the schematic.
There are additional parasitic report features as well just play around with the
tool.


For post layout simulation with parasitics you have to use
your extracted or refined extracted view.


Bernd


ponderboy wrote:

After extracting pararistic elment such as R and C,I want to
backanotation pararistic elment to schematic and do pararisric post
simulation,but cdsdoc told me that i need a MSPS licnese to run,so
could anyone tell me which feature or licnesedo i need to run MSPS?

 

[Bernd Fischer]

Correcting myself:

To do a backannotation to your schematic I think you have to create a
refined extracted view first.
Therefore you need the feature 34510 "Analog Environment".

Bernd

Bernd Fischer > wrote:

I think no extra license feature is required to do that or it's included
in the DFII or Assura features.

But be aware you can not do a post layout simulation on
your schematic with backannotated parasitics, this feature
is just a viewing option, which gives the designer a idea where
the parasitic elements are located in the schematic.
There are additional parasitic report features as well just play around
with the
tool.


For post layout simulation with parasitics you have to use
your extracted or refined extracted view.


Bernd

 

[fogh]

Bernd ,
are you 100% on that one ? IIRC have in 5.1 setups recently demo'ed to
end users backanotation of C and L to schematic without creating an
analog_extracted or running DCOP.
I am under the impression that the various options of assura >3.0 RCX
are more useful in refining/reducing than MSPS.

Bernd Fischer

wrote:
Correcting myself:

To do a backannotation to your schematic I think you have to create a
refined extracted view first.
Therefore you need the feature 34510 "Analog Environment".

Bernd

Bernd Fischer > wrote:

I think no extra license feature is required to do that or it's included
in the DFII or Assura features.

But be aware you can not do a post layout simulation on
your schematic with backannotated parasitics, this feature
is just a viewing option, which gives the designer a idea where
the parasitic elements are located in the schematic.
There are additional parasitic report features as well just play
around with the
tool.


For post layout simulation with parasitics you have to use
your extracted or refined extracted view.


Bernd

 

[Andrew Beckett]

You don't need to create an analog_extracted view first (i.e. a "build analog")
to do the backannotation. You do however have to do a DC simulation of the
extracted view in order to be able to backannotate the resistor values though
(in older versions this was not necessary, but the resistor value was just the
sum of all the resistors in that part of the parasitic network, which was of no
use to man or beast).

The main purpose of build analog is to allow selective parasitic inclusion,
without needing to re-run the Assura RCX run again with the appropriate options
to select just those nets. If you want to include all parasitics that Assura RCX
produced, there's no need to do build analog. For Diva it does some additional
housekeeping as well (sorts out globals, for example), so it may be needed there
- also, Diva does not have any means of doing selective net extraction, so you'd
have to do it via MSPS.

As for licensing, there used to be a separate product for MSPS, but that got
included in ADE (34510) since IC446 (i.e. since June 2000).

Regards,

Andrew.

On Mon, 03 Apr 2006 21:14:07 +0200, fogh <adff_at@xs4all_dot.nl> wrote:

Bernd ,
are you 100% on that one ? IIRC have in 5.1 setups recently demo'ed to
end users backanotation of C and L to schematic without creating an
analog_extracted or running DCOP.
I am under the impression that the various options of assura >3.0 RCX
are more useful in refining/reducing than MSPS.

Bernd Fischer
wrote:
Correcting myself:

To do a backannotation to your schematic I think you have to create a
refined extracted view first.
Therefore you need the feature 34510 "Analog Environment".

Bernd

Bernd Fischer > wrote:

I think no extra license feature is required to do that or it's included
in the DFII or Assura features.

But be aware you can not do a post layout simulation on
your schematic with backannotated parasitics, this feature
is just a viewing option, which gives the designer a idea where
the parasitic elements are located in the schematic.
There are additional parasitic report features as well just play
around with the
tool.


For post layout simulation with parasitics you have to use
your extracted or refined extracted view.


Bernd