which bit I loose

[Sridhar_Gadda]

Hi,

if I assign 4 bit wide register to 3 bit wide register, which bit I
loose MSB or LSB ?

thanks

Sridhar

 

[Karthikeyan Subramaniyam]

Sridhar_Gadda wrote:

Hi,

if I assign 4 bit wide register to 3 bit wide register, which bit I
loose MSB or LSB ?

thanks

Sridhar

Hi

I tried in VCS-MX simulator with the following simple example.
-------
reg [0:3] a;
reg [2:0] b;

initial a = 4'b1011;

initial begin
#1 b = a;
#10 $finish;
end
-------
In this case MSB a[0] was truncated.

If I changed the definition of 'a' as
-------
reg [3:0] a;
-------
then MSB a[3] was truncated.

HTH
-------
Karthikeyan Subramaniyam,
Design Verification Engineer,
TooMuch Semiconductor Solutions Pvt. Ltd.
www.toomuchsemi.com
A Bangalore based startup specialising on services in EDA & Verification.

 

[Andy Peters]

"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message news:<38f27fe8fb8a9f09528560af8546b148@localhost.talkaboutprogramming.com>...

Hi,

if I assign 4 bit wide register to 3 bit wide register, which bit I
loose MSB or LSB ?

The answer is: be explicit about your assignments, and you'll never
have to worry about which bits are truncated.

If I see code like yours in a code review, it gets marked in bold red
as BAD.

--a

 

[glen herrmannsfeldt]

Andy Peters wrote:

"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message news:<38f27fe8fb8a9f09528560af8546b148@localhost.talkaboutprogramming.com>...

if I assign 4 bit wide register to 3 bit wide register,
which bit I loose MSB or LSB ?

The answer is: be explicit about your assignments, and you'll never
have to worry about which bits are truncated.

If I see code like yours in a code review, it gets marked in bold red
as BAD.

For registers I agree, but considering that, at least when
synthesized, N bit adders generate N+1 bit sums, and it is
often convenient to assign them to N bit registers, this problem
comes up often. I am pretty sure in that case the MSB is lost,
as one would hope.

One I don't know, even though I have seen it done, is assigning
source[0:7] to sink[7:0] does it do it in pin order or numerical
order? (The one I saw wasn't verilog, so really doesn't apply here.)

-- glen

 

[Ensoul Chee]

I think this should be under your control.

You should make it clearly what should simulation tools should do.


"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message news:<38f27fe8fb8a9f09528560af8546b148@localhost.talkaboutprogramming.com>...

Hi,

if I assign 4 bit wide register to 3 bit wide register, which bit I
loose MSB or LSB ?

thanks

Sridhar

 

[mritun]

Hi Glen

Its the MSB that *always* gets lost when Lvalue is of lesser width than
Rvalue.

Naming the pins in left to right order (eg [3:0]) or right to left
order (eg [0:3]) doesn't mean anything. Its the MSB (left most pin(s) )
that get truncated.

And yeah, assignments happen in pin order rather than in numerical
order.

- Akhilesh

glen herrmannsfeldt wrote:

comes up often. I am pretty sure in that case the MSB is lost,
as one would hope.

One I don't know, even though I have seen it done, is assigning
source[0:7] to sink[7:0] does it do it in pin order or numerical
order? (The one I saw wasn't verilog, so really doesn't apply
here.)

 

[Andy Peters]

glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<clmkvv$uaf$1@gnus01.u.washington.edu>...

Andy Peters wrote:

"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message news:<38f27fe8fb8a9f09528560af8546b148@localhost.talkaboutprogramming.com>...

if I assign 4 bit wide register to 3 bit wide register,
which bit I loose MSB or LSB ?

The answer is: be explicit about your assignments, and you'll never
have to worry about which bits are truncated.

If I see code like yours in a code review, it gets marked in bold red
as BAD.

For registers I agree, but considering that, at least when
synthesized, N bit adders generate N+1 bit sums, and it is
often convenient to assign them to N bit registers, this problem
comes up often. I am pretty sure in that case the MSB is lost,
as one would hope.

The thing I learned from VHDL was to realize that this happens, and
sign-extend the operands. Fussy, yes, but correct

One I don't know, even though I have seen it done, is assigning
source[0:7] to sink[7:0] does it do it in pin order or numerical
order? (The one I saw wasn't verilog, so really doesn't apply here.)

Verilog assigns things by bit position and ignores the index number.
In other words, assigning source[0:7] to sink[7:0] gives you the
following:

sink[0] = source[7]
sink[1] = source[6]
...
sink[6] = source[1]
sink[7] = source[0]

Again, though, if you're doing such an assignment, you would do well
to be explicit about it and avoid confusion.

-a