which always block will infer to latch?

[mynewlifever@yahoo.com.cn]

Somebody told me that one of those two always blocks will infer to
latch. But I donnot know which one. I think both of them write all the
condition that will happen.Some books told me if you write code like
this
begin
if
else if
end
or like this
case:
state0:
state1:
endcase
will syn latches.But these two always blocks use else or default.So I
realy donot know which one.
I need help,please help me.Thank you!

the first always block:
always @(en or ina or inb)
begin
if(en)
begin
data_out = ina;
end
else
begin
data_out =inb;
end
end

the second always block:
input [3:0] data_in;
always @(data_in)
begin
case (data_in)
0: out1=1'b1;
1,3: out2 = 1'b1;
2,4,5,6,7: out3 = 1'b1;
default : out4 = 1'b1;
endcase
end

 

The 1st will not infer a latch, because data_out is set with all
conditions of en.

The 2nd will infer a latch (4 actually), because the output(s) are
sparsely set.

Think about it: In the 2nd example, what does out1 get set to if
data_in = 3 ???

There's one of your latches.

GH

 

[Markus Hagen]

ghelbig@lycos.com wrote:

The 2nd will infer a latch (4 actually), because the output(s) are
sparsely set.

Think about it: In the 2nd example, what does out1 get set to if
data_in = 3 ???
There's one of your latches.

This can easily be solved with default assignments before the
case-statement:

out1 = 1'b0;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b0;
always @(data_in)
begin
case (data_in)
0 : out1 = 1'b1;
1,3 : out2 = 1'b1;
2,4,5,6,7: out3 = 1'b1;
default : out4 = 1'b1;
endcase
end


Is there another recommendable way to achieve this?


Regards,
Markus

 

Markus Hagen wrote:

Is there another recommendable way to achieve this?

It's mostly a style question. What coding makes it most obvious what's
intended?

Another way to write it:

always @(data_in)
begin
case (data_in)
0 :
out1 = 1'b1;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b0;
1,3 :
out1 = 1'b0;
out2 = 1'b1;
out3 = 1'b0;
out4 = 1'b0;
2,4,5,6,7:
out1 = 1'b0;
out2 = 1'b0;
out3 = 1'b1;
out4 = 1'b0;
default :
out1 = 1'b0;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b1;
endcase
end

Myself, I would declare 'out' as a vector (out[3:0]) and the case
statement would look like:

2,4,5,6,7: out[3:0] = 4'b0100;

Again, this is a _style_ issue. Try to make the intended action
painfully obvious.

GH

 

[Ralf Hildebrandt]

Markus Hagen schrieb:

This can easily be solved with default assignments before the
case-statement:

out1 = 1'b0;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b0;
always @(data_in)
begin
case (data_in)
0 : out1 = 1'b1;
1,3 : out2 = 1'b1;
2,4,5,6,7: out3 = 1'b1;
default : out4 = 1'b1;
endcase
end

But then one gets _different_ behavior!

If it is acceptable, it is great, because removing latches / flipflops
and using just combinational logic is great.


Ralf

 

[Markus Hagen]

Ralf Hildebrandt wrote:

But then one gets _different_ behavior!

Sorry, of course you're right.

One could modify Helbig's solution:

always @(data_in)
begin
case (data_in)
0 :
out1 = 1'b1;
out2 = out2;
out3 = out3;
out4 = out4;
1,3 :
out1 = out1;
out2 = 1'b1;
out3 = out3;
out4 = out4;
2,4,5,6,7:
out1 = out1;
out2 = out2;
out3 = 1'b1;
out4 = out4;
default :
out1 = out1;
out2 = out2;
out3 = out3;
out4 = 1'b1;
endcase
end

Or as a vector:

2,4,5,6,7: out[3:0] = {out1, 1'b1, out3, out4};


But what does the optimizer do here?
The synthesis tool could infer latches again, since of course out3 =
out3 doesn't change anything.


Regards
Markus

 

Depends on the optimizer. Some deal well with latches, some don't.

At least with this example, it's obvious that you are creating latches.

GH

 

[Ralf Hildebrandt]

Markus Hagen schrieb:

But then one gets _different_ behavior!

always @(data_in)
begin
case (data_in)
0 :
out1 = 1'b1;
out2 = out2;
out3 = out3;
out4 = out4;
1,3 :
out1 = out1;
out2 = 1'b1;
out3 = out3;
out4 = out4;
2,4,5,6,7:
out1 = out1;
out2 = out2;
out3 = 1'b1;
out4 = out4;
default :
out1 = out1;
out2 = out2;
out3 = out3;
out4 = 1'b1;
endcase
end

This should be equal to the first solution. Assigning the value of the
variable to the variable itself is the behavior of a latch.
If a target does not support latches as primitive cells, they are build
using such a loop.

If it is possible to simplify the problem and remove the latches, it
will be a great advantage. But without knowledge about the problem it
can't be done.
If it is required to store a value, but latches are forbidden, then the
design has to be modified and flipflops have to be used.

Ralf