Whether is there a VHDL configuration like structure in Veri

[Robert Willy]

Hi,

I remember that there is a configuration structure in VHDL, i.e. select a architecture for an entity. Is there a similar structure in Verilog?

For example, there are two modules here. I want to use one based on a selection.


Thanks,





module regwrite(
output reg [3:0] rout,
input clk, in,
input [3:0] ctrl);
always @(posedge clk)
if(ctrl[0]) rout[0] <= in;
else if(ctrl[1]) rout[1] <= in;
else if(ctrl[2]) rout[2] <= in;
else if(ctrl[3]) rout[3] <= in;
endmodule



module regwrite(
output reg [3:0] rout,
input clk, in,
input [3:0] ctrl);
always @(posedge clk) begin
if(ctrl[0]) rout[0] <= in;
if(ctrl[1]) rout[1] <= in;
if(ctrl[2]) rout[2] <= in;
if(ctrl[3]) rout[3] <= in;
end
endmodule

 

[Johann Klammer]

On 08/15/2015 07:26 AM, Robert Willy wrote:

Hi,

I remember that there is a configuration structure in VHDL, i.e. select a architecture for an entity. Is there a similar structure in Verilog?

For example, there are two modules here. I want to use one based on a selection.


`ifdef perhaps?
Thanks,





module regwrite(
output reg [3:0] rout,
input clk, in,
input [3:0] ctrl);
always @(posedge clk)
if(ctrl[0]) rout[0] <= in;
else if(ctrl[1]) rout[1] <= in;
else if(ctrl[2]) rout[2] <= in;
else if(ctrl[3]) rout[3] <= in;
endmodule

I wonder what the other rout[] elements become?


module regwrite(
output reg [3:0] rout,
input clk, in,
input [3:0] ctrl);
always @(posedge clk) begin
if(ctrl[0]) rout[0] <= in;
I wonder, is rout[0] supposed to keep the previous value if ctrl[0] is not set?

<= in;
if(ctrl[2]) rout[2] <= in;
if(ctrl[3]) rout[3] <= in;
end
endmodule

 

[Pinhas Krengel]

Package, and record array in VHDL using free simulator GHDL.
1.The following short and simple VHDL tip shows the usage of a record array in VHDL. The small case is tested via the free VHDL simulator: GHDL.

2.The test case is made of two VHDL files: a small package and the test-bench. Part of the package is shown below:

The package my_package is

type enum_size is (ZERO,EIGHT,SIXTEEN, THIRTY_TWO);
type enum_direction is (RW, RD);

type reg is record
direction: enum_direction;
reg_data: std_logic_vector (31 downto 0);
reset_value: std_logic_vector (31 downto 0);
expected: std_logic_vector (31 downto 0);
size: enum_size;
end record;
type registers is array(255 downto 0) of reg;

1.The main part of the test-bench is the operation of the record array:

process(clk)
variable prt_cnt : integer := 10;
variable addrv : integer;
variable my_line : line;
begin
if(clk'event and clk = '1') then
da <= da + x"00000001";
addr <= addr + 2;
--
r_reg.reg_data <= da;
a_reg(addr).reg_data <= da;
if(prt_cnt /= 0) then
prt_cnt := prt_cnt-1;
if(addr > 0) then addrv := addr-2; else addrv := 0; end if;
write(my_line, string'("dbg "));
hwrite(my_line, a_reg(addrv).reg_data);
write(my_line, string'(" "));
write(my_line, addrv);
write(my_line, string'(" at "));
write(my_line, now);
writeline(output, my_line);
end if;
end if;
end process;

For more info please see
http://bknpk.ddns.net/my_web/MiscellaneousHW/vhdl_pkg_N_record_array.html