Where to insert pipeline delays

[DW]

This is a bit of a general question really and slightly philosophical. My
problem at the moment is how I should determine where to insert pipeline
delays (i.e. registers) in my sequential logic design. As far as simulating
goes, I could design the system to execute (almost) in a single instant of
time. This would enable me to check my transfer function is as I expected.
Obviously though, to improve throughput, I will have to insert pipeline
delays to stagger the various stages of processing, so I might insert one
between lets say two adder stages. This all seems a little arbitrary,
though and I'm not sure whether there are better rules to govern how this
should be done. Has anyone else had this problem? Should I just bang 'em
in and see how my timing simulation goes and tweak where necessary -
although doing this may involve adding unnecessary code to align control
parameters with the data flow etc. Maybe I'm making a rod for my own back.
Thanks for reading...

 

[glen herrmannsfeldt]

DW wrote:

This is a bit of a general question really and slightly philosophical. My
problem at the moment is how I should determine where to insert pipeline
delays (i.e. registers) in my sequential logic design. As far as simulating
goes, I could design the system to execute (almost) in a single instant of
time. This would enable me to check my transfer function is as I expected.
Obviously though, to improve throughput, I will have to insert pipeline
delays to stagger the various stages of processing, so I might insert one
between lets say two adder stages. This all seems a little arbitrary,
though and I'm not sure whether there are better rules to govern how this
should be done. Has anyone else had this problem?

(snip)

If you have a linear pipeline where all stages have the same
delay, you can then find the theoretical best place to put them.

There is some delay (mostly setup and hold time) to each stage,
and there is also the cost of the register itself. You can
then figure out where to put them to minimize cost, or maximize
throughput. For a more complicated system it will be a little
less obvious, but similar. You will usually want the delays
for each stage not to be too far off.

-- glen

 

[Marko]

Start with a speed goal. For example if you need 100MHz operation,
then you can only afford 10nS for any operation. Now you combine as
many operations as you can without exceeding your 10nS budget. If you
can do it all in a single stage, then there is no need for pipelining.
Otherwise insert stages as needed to acheive your speed goal.

If this is a theoritical problem (such as a school project), and you
are trying to extract maximum speed, then pipeline everything
initially, figure out your resulting speed, and then use that as you
speed goal following the steps above.

Just my opinion.

On Wed, 2 Jun 2004 18:00:00 +0100, "DW" <dave_wooff@hotmail.com>
wrote:

This is a bit of a general question really and slightly philosophical. My
problem at the moment is how I should determine where to insert pipeline
delays (i.e. registers) in my sequential logic design. As far as simulating
goes, I could design the system to execute (almost) in a single instant of
time. This would enable me to check my transfer function is as I expected.
Obviously though, to improve throughput, I will have to insert pipeline
delays to stagger the various stages of processing, so I might insert one
between lets say two adder stages. This all seems a little arbitrary,
though and I'm not sure whether there are better rules to govern how this
should be done. Has anyone else had this problem? Should I just bang 'em
in and see how my timing simulation goes and tweak where necessary -
although doing this may involve adding unnecessary code to align control
parameters with the data flow etc. Maybe I'm making a rod for my own back.
Thanks for reading...