Where is my power going!

R

Raf Karakiewicz

Guest
Hi,

I have a large analog chip which is consuming WAY more power than it
should. Is there any way I can simulate it over one period and print out
all the current values at all nodes at each time step? I need to figure
out where my power is going. Any ideas?



Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu
 
In short ... No!

You have a "large chip" -- major problem number 1.

You need to isolate the power losses somehow by stage or area or whatever.

It is possible that the power loss is being simulated, or it is not being
simulated at all.

How much is "WAY" ... orders of magnitiude? ... a few times ... does it
work at all ...

Does it always consume too much power? Or only in certian modes?

( Hard to guess the answer to your problem with so few details!)

Try the tried and true method of sub-dividing your problem, and checking
each half ...

-- G



"Raf Karakiewicz" <rafal@eecg.utoronto.ca> wrote in message
news:pine.GSO.4.58.0504141855320.11445@ducks.eecg.toronto.edu...
Hi,

I have a large analog chip which is consuming WAY more power than it
should. Is there any way I can simulate it over one period and print out
all the current values at all nodes at each time step? I need to figure
out where my power is going. Any ideas?



Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu
Click to expand...
 
Hi,

Thanks for your post. I was hoping to generatate a 2D power consumption
graph. This would help me analyze where the power is going, and once I
fixed everything I would use that kind of figure in my publications.

Thanks again,
Raf


G Vandevalk wrote:
In short ... No!

You have a "large chip" -- major problem number 1.

You need to isolate the power losses somehow by stage or area or whatever.

It is possible that the power loss is being simulated, or it is not being
simulated at all.

How much is "WAY" ... orders of magnitiude? ... a few times ... does it
work at all ...

Does it always consume too much power? Or only in certian modes?

( Hard to guess the answer to your problem with so few details!)

Try the tried and true method of sub-dividing your problem, and checking
each half ...

-- G



"Raf Karakiewicz" <rafal@eecg.utoronto.ca> wrote in message
news:pine.GSO.4.58.0504141855320.11445@ducks.eecg.toronto.edu...

Hi,

I have a large analog chip which is consuming WAY more power than it
should. Is there any way I can simulate it over one period and print out
all the current values at all nodes at each time step? I need to figure
out where my power is going. Any ideas?



Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu
Click to expand...
 
By fix, I assume you mean that you will understand the power loss and
modify the design to mimimize the loss at that location (assuming this
can be done with acceptable degradation of performance!)

Note that the simulation will pick some idealized generic process corner.
In real life, this is only close to the actual spot. It would be a mistake
to
tune the circuit to an exact optimal spot when the resuting circuit is very
sensitive (powerwise) to a small (expected) variation in any critical
parameter.

Understanding of how to tune the circuit for varied (monte-carlo, 3dB, ... )
process
parameters is ket to a robust design.

.....
Note also that power could "disappear" in areas where modeling is weak!

i.e. High freq. noise; Mismatched connections; unmodeled IR drop;
unexpected temp
at a hot spot could cause a modeling error ...

.... or the excursion of the model into unmodeled areas ... (i.e. not all
areas are modeled to the same accuracy)

Be careful and good luck on locating the top 3 unexpected power consumers.

-- G


"raf" <rafal_REMOVETHIS_@eecg.utoronto.ca> wrote in message
news:69WdnYKNutVewPnfRVn-jQ@rogers.com...
Hi,

Thanks for your post. I was hoping to generatate a 2D power consumption
graph. This would help me analyze where the power is going, and once I
fixed everything I would use that kind of figure in my publications.

Thanks again,
Raf


G Vandevalk wrote:
In short ... No!

You have a "large chip" -- major problem number 1.

You need to isolate the power losses somehow by stage or area or
whatever.

It is possible that the power loss is being simulated, or it is not
being
simulated at all.

How much is "WAY" ... orders of magnitiude? ... a few times ... does it
work at all ...

Does it always consume too much power? Or only in certian modes?

( Hard to guess the answer to your problem with so few details!)

Try the tried and true method of sub-dividing your problem, and checking
each half ...

-- G



"Raf Karakiewicz" <rafal@eecg.utoronto.ca> wrote in message
news:pine.GSO.4.58.0504141855320.11445@ducks.eecg.toronto.edu...

Hi,

I have a large analog chip which is consuming WAY more power than it
should. Is there any way I can simulate it over one period and print out
all the current values at all nodes at each time step? I need to figure
out where my power is going. Any ideas?



Raf Karakiewicz
Electrical Engineer
rafal@eecg.toronto.edu
Click to expand...
 
"G" == G Vandevalk <vdvalk@rogers.com> writes:
G> Date: Tue, 19 Apr 2005 11:23:42 -0400
Click to expand...

G> By fix, I assume you mean that you will understand the power
G> loss and modify the design to mimimize the loss at that
G> location (assuming this can be done with acceptable degradation
G> of performance!)

G> Note that the simulation will pick some idealized generic
G> process corner. In real life, this is only close to the actual
G> spot. It would be a mistake to tune the circuit to an exact
G> optimal spot when the resuting circuit is very sensitive
G> (powerwise) to a small (expected) variation in any critical
G> parameter.

G> Understanding of how to tune the circuit for varied
G> (monte-carlo, 3dB, ... ) process parameters is ket to a robust
G> design.

G> .... Note also that power could "disappear" in areas where
G> modeling is weak!

G> i.e. High freq. noise; Mismatched connections; unmodeled IR
G> drop; unexpected temp at a hot spot could cause a modeling
G> error ...

G> ... or the excursion of the model into unmodeled areas
G> ... (i.e. not all areas are modeled to the same accuracy)

G> Be careful and good luck on locating the top 3 unexpected power
G> consumers.

G> -- G

All very fine points, but I don't think ones that answer the original
question of how to find power consumed in every branch of a circuit.

To get power in a branch of a circuit, one could use MDL or even spectre
probes. But it would be impractical to do this for every branch in a
large circuit.

The other method would be to stop the transient at some point and
write a transient operating point file (in a text file), which can
then be processed using perl, awk or whatever people use to process
such files.

I have personally never used either of the above methods. So these are
conjectures, that in my opinion sound somewhat reasonable.

Regards
Satya

--
Remove XXX and YYY to get my address
 
On Tue, 19 Apr 2005 09:53:22 -0600, Satya Mishra <snmishra@XXXhotYYYpop.com>
wrote:

"G" == G Vandevalk <vdvalk@rogers.com> writes:

All very fine points, but I don't think ones that answer the original
question of how to find power consumed in every branch of a circuit.

To get power in a branch of a circuit, one could use MDL or even spectre
probes. But it would be impractical to do this for every branch in a
large circuit.

The other method would be to stop the transient at some point and
write a transient operating point file (in a text file), which can
then be processed using perl, awk or whatever people use to process
such files.

I have personally never used either of the above methods. So these are
conjectures, that in my opinion sound somewhat reasonable.

Regards
Satya
Click to expand...
Another thing you can do is to use the Outputs->Save All form, and
turn on saving of all power signals. Then after the simulation (on the
Results->Direct Plot->Main Form, you can plot the power results).

Caveat: if you have Verilog-A models, they'll only produce power if they
announce their power usage with the $pwr() statement.

Give it a try!

Regards,

Andrew.
 
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