Where does null statement go?

Guest
Hi,
I would ask where the following null statement goes?

I am using two module pattern to write a state machine.
The following are statements in a state:

when A =>
NextState <= A1;
case B(1 downto 0) is
when "00" =>
null;

when others =>
NextState <= A2;
end case;

Null statement remains at state A or go to default state A1?
Thank you.

Weng
 
Weng,
Null does not impact the assignment to NextState, so
based on your snippet, it will get the value A1 (from
the default statement). It works just like the
equivalent if statement:

when A =>
NextState <= A1;

if B(1 downto 0) /= "00" then
NextState <= A2;
end if ;

Regards,
Jim


Hi,
I would ask where the following null statement goes?

I am using two module pattern to write a state machine.
The following are statements in a state:

when A =
NextState <= A1;
case B(1 downto 0) is
when "00" =
null;

when others =
NextState <= A2;
end case;

Null statement remains at state A or go to default state A1?
Thank you.

Weng

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
Jim,
Thank you for your response.

In the following situation, where does null statement will go?
when A =>
-- NextState <= A1;
case B(1 downto 0) is
when "00" =>
null;

when others =>
NextState <= A2;
end case;

The default value statement is commented out.

Weng
 
Jim,
Good point!!!

Thank you very much.

I did an experience with ModelSim and found that if there is no default
value statement, it will remain at the same state without change.

Your response tells me why it will remain unchanged: a latch is used
for combinatorial logic: it must be avoided to reduce cost.

Weng
 
Jim,
When a default state is not specified in a state, compiler will
generate a latch.

I am interested why compiler generates a latch instead of assigning a
new value to the signal.

when A =>
-- NextState <= A1;
case B(1 downto 0) is
when "00" =>
null; <-- why cannot it generate NextState <= A without any
difference with latch;
when others =>
NextState <= A2;
end case
 
Hi Rick,
"when there is a condition where there is *no* assignment"

It means keep related signal unchanged <<-- That is most important
language meaning.

Using latch is one method, Assigning unchanged value to the signal to
let it has the same value and still a combinatorial signal is another.

I don't see why we cannot do it.

In another words, I mean user cannot see any differences between the
above two implementation, but the latter is much simpler and cost less
and usually is what designers want to.

Weng
 
wtx@umem.com wrote:
Hi Rick,
"when there is a condition where there is *no* assignment"

It means keep related signal unchanged <<-- That is most important
language meaning.

Using latch is one method, Assigning unchanged value to the signal to
let it has the same value and still a combinatorial signal is another.

I don't see why we cannot do it.

In another words, I mean user cannot see any differences between the
above two implementation, but the latter is much simpler and cost less
and usually is what designers want to.
Hmmm... If you are detecting the state of a signal and hold the value of
the signal to its same value, isn't that a latch??? This is known as
combinatorial feedback and is one way to make a latch. So the two
methods seem to produce the same results because they are the same
method.

Most of the time, the signal that is evaluated in a conditional is not
the object of the assignment. Normally one is being evaluated and the
other is being assigned. NextState <= f(CurState) as a concurrent
assignment and CurState <=NextState inside a clocked process. If you
assign CurState <= f(CurState) inside a clocked process, no latch is
generated. It is already describing a register.

Regardless, this is the way it is. If you fail to specify an concurrent
assignment for any conditional branches, a latch will be synthesized.
So fully specify your assignments! Simple, no?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Weng Tianxiang wrote:
I only read one case where a latch is used for Asynchronous FIFO. I
never see it elsewhere except compiler treats any missing assignment of
NextState as a latch or a register without an initial value when reset
is asserted.
It all depends of course whether you're talking about a combinatorial
process or a clocked process. In the latter case only FFs are inferred,
in the former case a latch will be created if a signal is not assigned a
value under all conditions.

Paul.
 
Weng,
Again, replace your case statement with an equivalent
if statement. What does it do?

Again seeing only this snippet, without the default
value, I see a latch. Of course if this is a clocked
process, then it will be a register with load enable.

Regards,
Jim

Jim,
Thank you for your response.

In the following situation, where does null statement will go?
when A =
-- NextState <= A1;
case B(1 downto 0) is
when "00" =
null;

when others =
NextState <= A2;
end case;

The default value statement is commented out.

Weng

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
wtx@umem.com wrote:
Jim,
When a default state is not specified in a state, compiler will
generate a latch.

I am interested why compiler generates a latch instead of assigning a
new value to the signal.

when A =
-- NextState <= A1;
case B(1 downto 0) is
when "00" =
null; <-- why cannot it generate NextState <= A without any
difference with latch;
when others =
NextState <= A2;
end case
It can if you tell it. But the null tells it to do nothing which means
"remember the last state" as in a latch.

A latch is inferred not when there is no default assignment, but when
there is a condition where there is *no* assignment. Having a default
assignment just provides an assignment for every condition.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Rick,
"If you are detecting the state of a signal and hold the value of
the signal to its same value, isn't that a latch???"

Answer is no.

For example, there is state machine that has 10 states. And designer
uses 2 parts of pattern to design a state machine, one is for
NextState, another for registers;

Now I often met the situations: where I forgot to assign a value to
NextState. Then compiler claims it will establish a latch.

I think it can do another way:
For a missing assignment of NextState, it can "add an NextState
assignment statement" at the missing place with current state value. So
NextState doesn't have to become a latch. Usually latch is more costly
than combinatorial logic for NextState as compiler knows so that it
often gives warning: a latch is established.

Actually a latch reference usually means a code error, not the desire
of programmers.

I only read one case where a latch is used for Asynchronous FIFO. I
never see it elsewhere except compiler treats any missing assignment of
NextState as a latch or a register without an initial value when reset
is asserted.

Weng
 
Weng Tianxiang wrote:
Rick,
"If you are detecting the state of a signal and hold the value of
the signal to its same value, isn't that a latch???"

Answer is no.

For example, there is state machine that has 10 states. And designer
uses 2 parts of pattern to design a state machine, one is for
NextState, another for registers;

Now I often met the situations: where I forgot to assign a value to
NextState. Then compiler claims it will establish a latch.

I think it can do another way:
For a missing assignment of NextState, it can "add an NextState
assignment statement" at the missing place with current state value. So
NextState doesn't have to become a latch. Usually latch is more costly
than combinatorial logic for NextState as compiler knows so that it
often gives warning: a latch is established.
But that is what you don't seem to understand. The compiler has no way
of knowing the "current" state of NextState. Your case statement is
looking at CurState not NextState! Unless you knew something more about
NextState than is apparent in the code, (which you, the designer, will
know) there is no way to "keep" the current value other than to use a
latch.

I will say this once very clearly and then I want you to stop posting
about it until you understand. There is no way for the compiler to know
what state you want assigned to NextState based on the value of
CurState. YOU know what you want, but the tool does not know that
CurState and NextState are related by anything other than the code you
write. If you don't give the code a default, the tool can't know what
you want.

If you want NextState to default to the value of CurState, then you
should use a default assignment... NextState <= CurState; Then if you
omit an assignment, the tool will know what you want.


Actually a latch reference usually means a code error, not the desire
of programmers.

I only read one case where a latch is used for Asynchronous FIFO. I
never see it elsewhere except compiler treats any missing assignment of
NextState as a latch or a register without an initial value when reset
is asserted.
If you don't want a latch, then don't specify one. A missing assignment
specifies a latch.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 

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