When tool synthesize, does all logic convert into NAND gate?

< It's beginner level question.>
Hi, I've heard that all logic is converted into NAND logic.
Is it right?
I know any logic "can" be converted into NAND or NOR gate.
But if all are converted into NAND, are there some advantages?
Thanks.

 

[John_H]

<jycho@gatech.edu> wrote in message
news:1171576684.138385.279690@j27g2000cwj.googlegroups.com...

It's beginner level question.
Hi, I've heard that all logic is converted into NAND logic.
Is it right?
I know any logic "can" be converted into NAND or NOR gate.
But if all are converted into NAND, are there some advantages?
Thanks.

If you target FPGAs, there's no reason to decompose to NAND gates since the
target silicon isn't NAND functionality.

In ASICs, multi-input structures are best implemented with multiple n and p
type transistors in one structure, certainly not a multitude of NANDs. In
these structures one could cite transistor count in NAND equivalents though
the whole "gate counting" exercise was lost on me early in my career.

I know of no benefits to NAND decomposition.

 

[ajjc]

On Feb 15, 1:58 pm, j...@gatech.edu wrote:

It's beginner level question.
Hi, I've heard that all logic is converted into NAND logic.
Is it right?
I know any logic "can" be converted into NAND or NOR gate.
But if all are converted into NAND, are there some advantages?
Thanks.

There are no user-level advantages, but some of the synthesis and
mapping tools turn the post-minimized combinatorial clouds of logic
between
register banks into 2-input nand gates to make it easier for the
packing-with-timing minimization tools to map to gate libraries, for
whatever technology is being targeted. "Easier" is, of course
relative, but is is a heck of a lot cleaner to map from a simple
network to a more complex one...from an algorithmic point of view.
The end user usually doesn't care and doesn't know as long as they
can't do any better mapping by hand or by using a competitors tool
chain.

alan