"when others" question

Hello,

I've rather foolishly missed out a "when others" statement in a state
machine that I have recently coded. After reading a few posts in this
group it seems that the "when others" statement was redundant anyway,
due to the coding style I implemented (thanks to a post from Jonathan
Bromley for pointing me in the direction of using variables to define
state transitions).
Have I understood this correctly, do I not need the "when others"
statement as all the state transitions are covered within the code? As
the code does not have 2^n states, does the synthesis tool not require
some form of default statement to get the state machine back to a
known state (in case of electrical problems causing dodgy state
transitions, etc.)
I've posted some sample code below to show what I mean

thanks for any help,
Will

------------------------------------------------------------------------------

process (clk, reset)
type statetype is (aa, bb, cc, dd, ee);
variable state: statetype;
begin
if reset = '1' then
state := aa;
sigout <= "00001";
elsif rising_edge(clock) then
case state is
when aa =>
state := bb;
when bb =>
state := cc;
when cc =>
state := dd;
when dd =>
state := ee;
when ee =>
state := aa;
end case;

case state is
when aa =>
sigout <= "00001";
when bb =>
sigout <= "00001";
when cc =>
sigout <= "00001";
when dd =>
sigout <= "00001";
when ee =>
sigout <= "00001";
when others =>
sigout <= "11111";
end case;
end if;
end process;

 

[KJ]

On Jan 29, 4:31 pm, william.m...@yahoo.co.uk wrote:

Hello,

Have I understood this correctly, do I not need the "when others"
statement as all the state transitions are covered within the code? As
the code does not have 2^n states,

How many 'unreachable' states are needed is a function of how the
synthesis tool implements the signal. In your case with 5 states
defined, there might be a total of 8 potential states (3 invalid ones)
if 'state' is implemented with binary coding. Or it could have a
total of 32 potential states (27 invalid ones) if 'state' is
implemented as a one hot state machine.

does the synthesis tool not require
some form of default statement to get the state machine back to a
known state (in case of electrical problems causing dodgy state
transitions, etc.)

The synthesis tool does not require them but, depending on where your
design is destined for and what system recovery mechanisms are
available, your overall design might need them. For those cases that
really do need auto-recovery, you wouldn't be able to get away with
using an enumerated type in the first place because of these types of
concerns.

Another 'problem' can be that, even if you code for those other
states, the synthesis tool can optimize them out so even if you put
the code in there, if the tool can logically prove that there are no
paths to 'other' states, it can optimize out the "If I'm in an illegal
state then go idle" logic. Quartus has a synthesis option to allow/
prohibit this particular type of optimization, other tools may have as
well.

Play around with your synthesis tool and a sample design a bit to see
what is actually produced.

Kevin Jennings

 

[Peter]

Have I understood this correctly, do I not need the "when others"
statement as all the state transitions are covered within the code?

The "when others" is not needed when all states are covered. You will
probably get a warning in the synthesis logg if you use it.

the code does not have 2^n states, does the synthesis tool not require
some form of default statement to get the state machine back to a
known state (in case of electrical problems causing dodgy state
transitions, etc.)

From VHDL point of view you dont have 2^n states, just aa...ee i.e. 5
states.
Synthesis may decide coding the states in a number of ways, one-hot,
binary etc.
The "when others" clause does not generate logic to force the machine
back from "unused" states. Please refer to the Synplicity application
note "Designing Safe VHDL State Machines with Synplify".

/Peter