What's wrong with this verilog?

[Davy]

Hi all,
I want to use OVL (http://www.eda.org/ovl/) to start learning assert.
Verilog version was used.
The .h and .vlib file has been changed to .v.
But the file seems have compile error.

(Modelsim 5.6)ERROR: D:/Modeltech_5.6/test/ovl_task.v(1): near "task":
expecting:
MACROMODULE MODULE PRIMITIVE (*

//------- part of ovl_task.h-----------
task ovl_error;
input [8*63:0] err_msg;
begin
error_count = error_count + 1;
`ifdef ASSERT_MAX_REPORT_ERROR
if (error_count <= `ASSERT_MAX_REPORT_ERROR)
`endif
$display("OVL_ERROR : %s : %s : %0s : severity %0d : time %0t :
%m",
assert_name, msg, err_msg, severity_level, $time);
if (severity_level == 0) ovl_finish;
end
endtask
//-------------------------------------

Three files have been packeted
(assert_always.vlib,ovl_header.h,ovl_task.h).

Any suggestions will be appreciated!
Best regards,
Davy

 

[Davy]

Hi Chris,

I copy ovl_task to assert_xxx.v, set some Macro. And all O.K.!

Thanks!
Davy