what's wrong in this code

[Sridhar_Gadda]

Hi,

I have written a simple code for D flipflop and output is feedback to
input but the results are not the same ...I suppose for every positive
edge clk. q = d , which means output is connected back to input. but q
graph always shows zero.......can anybody comment on what am I doing wrong
here

module d_flipflop_in_loop (q, d, clk);
output q;
input d, clk;
reg q;

always @(posedge clk)
q <= d;

endmodule


module test_d_flipflop_in_loop;
reg Q, D, CLK;
d_flipflop_in_loop dff( , D, CLK);
initial
begin
D = 1'b1;
CLK = 1'b0;
end
always
#5 CLK = ~CLK;
initial
#100 $finish;

endmodule

with regards ,

sridhar

 

[Sridhar_Gadda]

Hi everyone,
I checked with both simulators cadence-xL and Verilogger pro, both shows
the same results. when I declare Q in d_flipflop_in_loop dff( , D, CLK);
and in compilation errors shows "illegal port declaration" when Q is not
declared at reg Q, D, CLK; errors shows "Q" has not declared.

The above program compiles perfectly but results are unsual. The result
suppose to be D = 1 whenever CLK goes high.

suggestion are welcome.

regards

sridhar

 

[John_H]

"Sridhar_Gadda" <sridhargadda@yahoo.com> wrote in message
news:f973c7a9646af2d1d34a9710a5f03edd@localhost.talkaboutprogramming.com...

Hi,

I have written a simple code for D flipflop and output is feedback to
input but the results are not the same ...I suppose for every positive
edge clk. q = d , which means output is connected back to input. but q
graph always shows zero.......can anybody comment on what am I doing wrong
here
[snip]

[was]
module test_d_flipflop_in_loop;
reg Q, D, CLK;
d_flipflop_in_loop dff( , D, CLK);
[is]
module test_d_flipflop_in_loop;
wire Q;
reg D, CLK;
d_flipflop_in_loop dff(Q, D, CLK);
[works]

 

[Karthikeyan]

Sridhar_Gadda wrote:

Hi,

I have written a simple code for D flipflop and output is feedback to
input but the results are not the same ...I suppose for every positive
edge clk. q = d , which means output is connected back to input. but q
graph always shows zero.......can anybody comment on what am I doing wrong
here

module d_flipflop_in_loop (q, d, clk);
output q;
input d, clk;
reg q;

always @(posedge clk)
q <= d;

endmodule


module test_d_flipflop_in_loop;
reg Q, D, CLK;
d_flipflop_in_loop dff( , D, CLK);
initial
begin
D = 1'b1;
CLK = 1'b0;
end
always
#5 CLK = ~CLK;
initial
#100 $finish;

endmodule

with regards ,

sridhar

Hi

I need to clarify something with U.

First one is, Which simulator did U use?
second Which 'q' U are mentioning? In diff or testbench?
third why didn't U get the design output in testbench? ie.,
'Q' is not given in the instance parameter.

Give Q in the instance parameter like
d_flipflop_in_loop dff( Q, D, CLK);
it will work fine

by
karthik

 

[m]

On Tue, 12 Oct 2004 08:03:17 -0400, "Sridhar_Gadda"
<sridhargadda@yahoo.com> wrote:

module test_d_flipflop_in_loop;
reg Q, D, CLK;
d_flipflop_in_loop dff( , D, CLK);
initial
begin
D = 1'b1;
CLK = 1'b0;
end
always
#5 CLK = ~CLK;
initial
#100 $finish;

endmodule

In your testbench you need declare a wire Q and connect it to the Q
output of the dff instantiation. Right now, the Q output of the flop
is not visible at all when you look at the signals at the top level.

ie.

reg D, CLK;
wire Q;
d_flipflop_in_loop dff(Q, D, CLK);

etc.