B
bill
Guest
Hi,
In using Xilinx Virtex2 chip, I wonder what's teh general rule to
instantiate a global timing buffer.
If I use a DCM to do some clock divide and use the generated one to
driver in-chip design, I should add a buffer to the DCM output. But
how about my DCm i used to de-skew the clock, meaning clkin is in-chip
clock, while clkfb is off-chip clock, and clk0 going off-chip again,
it seems in this case, I do not have to add a buffer to clk0. but is
there any rule here...
In using Xilinx Virtex2 chip, I wonder what's teh general rule to
instantiate a global timing buffer.
If I use a DCM to do some clock divide and use the generated one to
driver in-chip design, I should add a buffer to the DCM output. But
how about my DCm i used to de-skew the clock, meaning clkin is in-chip
clock, while clkfb is off-chip clock, and clk0 going off-chip again,
it seems in this case, I do not have to add a buffer to clk0. but is
there any rule here...