What's the easy way to look up for a subvector in Verilog?

[Mr. Ken]

For example, now I have a 256-bit vector, I need to look up four bit at a
time,
the base location is indicated by variable t0. I prefer to have codes as
concise
as possible since complex "case" statements are too troublesome.

TIA


assign box = {
{4'd13}, {4'd2}, {4'd8}, {4'd4}, {4'd6}, {4'd15}, {4'd11}, {4'd1}, {4'd10},
{4'd9}, {4'd3}, {4'd14}, {4'd5}, {4'd0}, {4'd12}, {4'd7},
{4'd1}, {4'd15}, {4'd13}, {4'd8}, {4'd10}, {4'd3}, {4'd7}, {4'd4}, {4'd12},
{4'd5}, {4'd6}, {4'd11}, {4'd0}, {4'd14}, {4'd9}, {4'd2},
{4'd7}, {4'd11}, {4'd4}, {4'd1}, {4'd9}, {4'd12}, {4'd14}, {4'd2}, {4'd0},
{4'd6}, {4'd10}, {4'd13}, {4'd15}, {4'd3}, {4'd5}, {4'd8},
{4'd2}, {4'd1}, {4'd14}, {4'd7}, {4'd4}, {4'd10}, {4'd8}, {4'd13}, {4'd15},
{4'd12}, {4'd9}, {4'd0}, {4'd3}, {4'd5}, {4'd6}, {4'd11}};

assign t0 = (cond) ? 6'b00001 : variable;
assign s0 = box[{t0, 2'b11}:{t0, 2'b00}];

 

[John Penton]

Mr. Ken wrote:

For example, now I have a 256-bit vector, I need to look up four bit
at a time,
the base location is indicated by variable t0. I prefer to have codes
as concise
as possible since complex "case" statements are too troublesome.

TIA


assign box = {
{4'd13}, {4'd2}, {4'd8}, {4'd4}, {4'd6}, {4'd15}, {4'd11}, {4'd1},
{4'd10}, {4'd9}, {4'd3}, {4'd14}, {4'd5}, {4'd0}, {4'd12}, {4'd7},
{4'd1}, {4'd15}, {4'd13}, {4'd8}, {4'd10}, {4'd3}, {4'd7}, {4'd4},
{4'd12}, {4'd5}, {4'd6}, {4'd11}, {4'd0}, {4'd14}, {4'd9}, {4'd2},
{4'd7}, {4'd11}, {4'd4}, {4'd1}, {4'd9}, {4'd12}, {4'd14}, {4'd2},
{4'd0}, {4'd6}, {4'd10}, {4'd13}, {4'd15}, {4'd3}, {4'd5}, {4'd8},
{4'd2}, {4'd1}, {4'd14}, {4'd7}, {4'd4}, {4'd10}, {4'd8}, {4'd13},
{4'd15}, {4'd12}, {4'd9}, {4'd0}, {4'd3}, {4'd5}, {4'd6}, {4'd11}};

assign t0 = (cond) ? 6'b00001 : variable;
assign s0 = box[{t0, 2'b11}:{t0, 2'b00}];

Not exactly pretty, but what about something like:

assign temp = box >> {t0,2'b00};
assign s0 = temp[3:0];

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.

 

[John_H]

Mr. Ken wrote:

For example, now I have a 256-bit vector, I need to look up four bit at a
time,
the base location is indicated by variable t0. I prefer to have codes as
concise
as possible since complex "case" statements are too troublesome.

TIA


assign box = {
4'd13, 4'd02, 4'd08, 4'd04, 4'd06, 4'd15, 4'd11, 4'd01, 4'd10,
4'd09, 4'd03, 4'd14, 4'd05, 4'd00, 4'd12, 4'd07,
4'd01, 4'd15, 4'd13, 4'd08, 4'd10, 4'd03, 4'd07, 4'd04, 4'd12,
4'd05, 4'd06, 4'd11, 4'd00, 4'd14, 4'd09, 4'd02,
4'd07, 4'd11, 4'd04, 4'd01, 4'd09, 4'd12, 4'd14, 4'd02, 4'd00,
4'd06, 4'd10, 4'd13, 4'd15, 4'd03, 4'd05, 4'd08,
4'd02, 4'd01, 4'd14, 4'd07, 4'd04, 4'd10, 4'd08, 4'd13, 4'd15,
4'd12, 4'd09, 4'd00, 4'd03, 4'd05, 4'd06, 4'd11 };

assign t0 = (cond) ? 6'b00001 : variable;
assign s0 = box[{t0, 2'b00} +: 4];

Verilog2001 has the helpful construct that I've edited into s0 above.