What's the differences between translation_* and synthesis_*

[Peng Yu]

Hi,

Does somebody know what the differences between "// synopsys
translation_off" and "// synopsys synthesis_off" is?
I don't see much difference between them, except "// synopsys
translation_off" is controlled by hdlin_translate_off_skip_text.

Peng

 

[Alan Fitch]

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views of Doulos Ltd., unless specifically stated.

"Peng Yu" <yupeng_@hotmail.com> wrote in message
news:d7b3726c.0308110657.241dc736@posting.google.com...

Hi,

Does somebody know what the differences between "// synopsys
translation_off" and "// synopsys synthesis_off" is?
I don't see much difference between them, except "// synopsys
translation_off" is controlled by hdlin_translate_off_skip_text.

I'm sure it's mentioned in the manuals somewhere, but
basically translate_on/off disables the code between the comments
completely (it's effectively completely hidden from parsing and
synthesis).

synthesis_on/off still lets the tool parse the VHDL, but disables
synthesis.

For instance, this is fine

// synopsys translate_off
the tool will ignore any old rubbish I write here
// synopsys translate_on

While this will cause an error

// synopsys synthesis_off
I should have written valid Verilog in here - Doh!
// synopsys synthesis_on

regards

Alan

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[Peng Yu]

The following passages are what the manual says. It seems that what
you said is true when hdlin_translate_off_skip_text is set for true.


To isolate simulation-specific code and prevent the code from being
interpreted for synthesis, use the synthesis_off and synthesis_on
compiler directives. The code between the synthesis_off and
synthesis_on boundaries will be checked for syntax.
Example C-7 Using the synthesis_off and synthesis_on Compiler
Directives
//synopsys synthesis_off
.... //Simulation only code
//synopsys synthesis_on


To isolate simulation-specific code and prevent the code from being
interpreted for synthesis, use the translate_off and translate_on
compiler directives. The text between the translate_off and
translate_on boundaries will be checked for syntax unless the variable
hdlin_translate_off_skip_text is set for true.
Example C-8 Using the translate_off and translate_on Compiler
Directives
//synopsys translate_off
.... //Simulation only code
//synopsys translate_on

"Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<bhaatp$gkp$1$8302bc10@news.demon.co.uk>...

I'm sure it's mentioned in the manuals somewhere, but
basically translate_on/off disables the code between the comments
completely (it's effectively completely hidden from parsing and
synthesis).

synthesis_on/off still lets the tool parse the VHDL, but disables
synthesis.

For instance, this is fine

// synopsys translate_off
the tool will ignore any old rubbish I write here
// synopsys translate_on

While this will cause an error

// synopsys synthesis_off
I should have written valid Verilog in here - Doh!
// synopsys synthesis_on