What's RTL ? What's behavioral level in Verilog

[Kecheng]

I know RTL is the register level, but I'm confusing that what kind of
code is RTL, what belongs to the behavioral level ? Can anyone give me
an example to distinguish these two level? That will be very helpful
for me.

Thanks a bunch!

 

[Evan Lavelle]

A link to this article ('Abstraction Levels and Hardware Design')
turned up in my inbox this morning:

http://www.edadesignline.com/showArticle.jhtml?articleID=201001753

I read the first line of the 'RTL' section before posting the link,
which is:

The most widely used language for writing RTL code is Verilog. RTL code can also be written in SystemC.

This is probably a good reason not to read any more, but YMMV.

Evan

 

[Mike Treseler]

Evan Lavelle wrote:

A link to this article ('Abstraction Levels and Hardware Design')
turned up in my inbox this morning:
http://www.edadesignline.com/showArticle.jhtml?articleID=201001753
I read the first line of the 'RTL' section before posting the link,
which is:
The most widely used language for writing RTL code is Verilog. RTL code can also be written in SystemC.
This is probably a good reason not to read any more, but YMMV.

My mileage is exactly the same.
RTL is a subject for authors, not engineers.
Jonathan's comments from 1999 still ring true:
http://groups.google.com/groups?q=behavioural+vs+rtl+verilog+make-work


-- Mike Treseler

 

[Harrkev]

On Jul 17, 10:11 pm, Kecheng <kecheng...@gmail.com> wrote:

I know RTL is the register level, but I'm confusing that what kind of
code is RTL, what belongs to the behavioral level ? Can anyone give me
an example to distinguish these two level? That will be very helpful
for me.

Thanks a bunch!

I am just beginning Verilog, but have years of experience with VHDL.

To me, if it is synthesizable, it is gate level. That might not be
technically true, but it is close enough. If it can be made into
gates, it can get the job done. Let the professors argue over how
many verilog faries can dance on the head of a pin.

In general (and this is just my opinion), if you stick to plain
assigns (with the occasional "? :" thrown in), and always statements
with assignments, if's, and case's, then it can turn to gates -- as
long as you leave any hashes ("#") out of there. Also make sure to
stick to "hardware" data types, such as wire and reg (I know that
SystemVerilog has some fancier stuff).

I guess the textbook definition is that RTL describes how to BUILD the
device, while behavioral describes how it ACTS. When you have been
doing this long enough, they start to look the same

 

[Manickam]

My understanding:
* RTL coding is done to design the actual hardware.
Code should be 'synthesis-able'.
Which means no tasks, time delays, event waits are allowed.
Signals in always blocks should not be driven in multiple places.
Efficient usage of registers and memory is necessary to optimise cost
of the final chip.

* Behavioral code is done to just model the process/interface or any
other process involving software and external systems. The code need
not implement everything in fine detail. Only the different features
to simulate a particular input or output is reqd. How the data is
processed or stored are not important. Engineers need not worry about
the equivalent logic inferred; behavioral code is intended only for
simulation purpose and is never going to be synthesized. Initial
blocks, tasks, events, wait etc are hence behavioral code.

Behavioral code is easier compared to RTL.
Well, the opinion depends upon which side you are!! ;-)




On Jul 19, 10:15 pm, Harrkev <kevin.harrel...@gmail.com> wrote:

On Jul 17, 10:11 pm, Kecheng <kecheng...@gmail.com> wrote:

I know RTL is the register level, but I'm confusing that what kind of
code is RTL, what belongs to the behavioral level ? Can anyone give me
an example to distinguish these two level? That will be very helpful
for me.

Thanks a bunch!

I am just beginning Verilog, but have years of experience with VHDL.

To me, if it is synthesizable, it is gate level. That might not be
technically true, but it is close enough. If it can be made into
gates, it can get the job done. Let the professors argue over how
many verilog faries can dance on the head of a pin.

In general (and this is just my opinion), if you stick to plain
assigns (with the occasional "? :" thrown in), and always statements
with assignments, if's, and case's, then it can turn to gates -- as
long as you leave any hashes ("#") out of there. Also make sure to
stick to "hardware" data types, such as wire and reg (I know that
SystemVerilog has some fancier stuff).

I guess the textbook definition is that RTL describes how to BUILD the
device, while behavioral describes how it ACTS. When you have been
doing this long enough, they start to look the same

 

[Yottameter]

Gate level code is RTL code that has been synthesized, not code that is
able to be synthesized.

Harrkev wrote:

On Jul 17, 10:11 pm, Kecheng <kecheng...@gmail.com> wrote:

I know RTL is the register level, but I'm confusing that what kind of
code is RTL, what belongs to the behavioral level ? Can anyone give me
an example to distinguish these two level? That will be very helpful
for me.

Thanks a bunch!


I am just beginning Verilog, but have years of experience with VHDL.

To me, if it is synthesizable, it is gate level. That might not be
technically true, but it is close enough. If it can be made into
gates, it can get the job done. Let the professors argue over how
many verilog faries can dance on the head of a pin.

In general (and this is just my opinion), if you stick to plain
assigns (with the occasional "? :" thrown in), and always statements
with assignments, if's, and case's, then it can turn to gates -- as
long as you leave any hashes ("#") out of there. Also make sure to
stick to "hardware" data types, such as wire and reg (I know that
SystemVerilog has some fancier stuff).

I guess the textbook definition is that RTL describes how to BUILD the
device, while behavioral describes how it ACTS. When you have been
doing this long enough, they start to look the same

 

[parag_paul@hotmail.com]

If the behavioral code is not going to be a input to the DC, why will
you take pains to write it, ( I mean yes, you will have to write
more )

SInce one your simulation says it is all correct, then you revert back
to coding it in RTL style . Why so ?

Why not start with RTL coding itself. It wont hurt later on .
I think , behavioral is good for test bench and generating all the
test vectors.It works fine there

 

[Yottameter]

That is true for most digital designs, you generally always create
verilog especially targeting a FPGA. If you are doing a mixed signal IC,
your company might not want to spend a lot of money on a mixed signal
simulator, so you might generate a verilog model of an analog block and
replace it later with the custom version. Also memories from vendors
typically are not synthesized in the traditional sense.


parag_paul@hotmail.com wrote:

If the behavioral code is not going to be a input to the DC, why will
you take pains to write it, ( I mean yes, you will have to write
more )

SInce one your simulation says it is all correct, then you revert back
to coding it in RTL style . Why so ?

Why not start with RTL coding itself. It wont hurt later on .
I think , behavioral is good for test bench and generating all the
test vectors.It works fine there