What's my mistake? Combinatorial decision

[TC2]

I must be missing something simple but it looks to me like these two cases
should be the same (can you say De Morgan?):

if (hndshk_to_fpga | inc_ndx | rst_ndx) begin
//do nothing
end
else begin
hndshk_from_motor = 0;
end



if (~hndshk_to_fpga & ~inc_ndx & ~rst_ndx) begin
hndshk_from_motor = 0;
end
else begin
//do nothing
end


Signal hndshk_to_fpga is a 1-bit input. Signals inc_ndx and rst_ndx are
1-bit registers. Example 1 works, example 2 doesn't.

Thanks,
Tom

 

[Clint Olsen]

In article <vhdmchtgbc8n5a@corp.supernews.com>, TC2 wrote:

if (hndshk_to_fpga | inc_ndx | rst_ndx) begin
//do nothing
end
else begin
hndshk_from_motor = 0;
end

if (~hndshk_to_fpga & ~inc_ndx & ~rst_ndx) begin
hndshk_from_motor = 0;
end
else begin
//do nothing
end

Looks like you blew DeMorgan's Law. Remember that DeMorgan's Law shows you
how to push negation bubbles across gates:

(ab)' = a' + b' (1)
(a + b)' = a'b' (2)

You need to get your first equation into a form that fits this:

a + b + c = ((a + b + c)')' # (a')' = a
((a + b + c)')' = (a'b'c')' # apply (2) to innermost negation

So, you need to invert your entire expression in your second example.

-Clint

 

[Andy Peters]

"TC2" <neinspam.tomcantlon@vispath.com> wrote in message news:<vhdmchtgbc8n5a@corp.supernews.com>...

I must be missing something simple but it looks to me like these two cases
should be the same (can you say De Morgan?):

if (hndshk_to_fpga | inc_ndx | rst_ndx) begin
//do nothing
end
else begin
hndshk_from_motor = 0;
end



if (~hndshk_to_fpga & ~inc_ndx & ~rst_ndx) begin
hndshk_from_motor = 0;
end
else begin
//do nothing
end


Signal hndshk_to_fpga is a 1-bit input. Signals inc_ndx and rst_ndx are
1-bit registers. Example 1 works, example 2 doesn't.

Are any of the inputs X or Z at any time?

--a

 

[Kevin Neilson]

I don't think you have a DeMorganization error; it's just a matter of when
you assign things. Let me rephrase your logic:

case 1) if (a); else b=0;

case 2) if (~a) b=0;

In case 1, b only gets assigned when a is true. In case 2, b only gets
assigned when a is false. Both are equivalent in a manner, because when b
is assigned, it is always assigned to a; it's just a matter of when it gets
assigned. There seems to be some code missing in your snippet, because you
don't show when the output gets a value of 1. That code should be in the
same process, because it's poor practice to assign a variable in two
processes unless it's nonsynthesizable test code.

-Kevin

"TC2" <neinspam.tomcantlon@vispath.com> wrote in message
news:vhdmchtgbc8n5a@corp.supernews.com...

I must be missing something simple but it looks to me like these two cases
should be the same (can you say De Morgan?):

if (hndshk_to_fpga | inc_ndx | rst_ndx) begin
//do nothing
end
else begin
hndshk_from_motor = 0;
end



if (~hndshk_to_fpga & ~inc_ndx & ~rst_ndx) begin
hndshk_from_motor = 0;
end
else begin
//do nothing
end


Signal hndshk_to_fpga is a 1-bit input. Signals inc_ndx and rst_ndx are
1-bit registers. Example 1 works, example 2 doesn't.

Thanks,
Tom

 

[nospam]

"TC2" <neinspam.tomcantlon@vispath.com> wrote:

if (hndshk_to_fpga | inc_ndx | rst_ndx) begin
//do nothing
end
else begin
hndshk_from_motor = 0;
end


if (~hndshk_to_fpga & ~inc_ndx & ~rst_ndx) begin
hndshk_from_motor = 0;
end
else begin
//do nothing
end

Signal hndshk_to_fpga is a 1-bit input. Signals inc_ndx and rst_ndx are
1-bit registers.

They are equivalent.

Example 1 works, example 2 doesn't.

What you gave us would both be optimised away. Your problem is with what
you didn't give us or (less likely) with your tools.

 

[Clint Olsen]

In article <slrnbhe4om.22qb.clint@poly.0lsen.net>, Clint Olsen wrote:

Looks like you blew DeMorgan's Law. Remember that DeMorgan's Law shows you
how to push negation bubbles across gates:

Whoops, I didn't read closely enough to notice you swapped the if/else
blocks, so it looks like it should work.

-Clint

 

[Jim Wu]

In your first if-else block, hndshk_from_motor = 0 if all inputs are not 1.
(they could be x or z)

In the second if-else block, hndshk_from_motor = 0 if and only if all inputs
are 0s.

So if there are any 'x' or 'z' in yout inputs, you would see simulation
mismatch, but the synthesis result should be the same.

Jim
jimwu88NOOOOOSPAM@yahoo.com

"TC2" <neinspam.tomcantlon@vispath.com> wrote in message news:<vhdmchtgbc8n5a@corp.supernews.com>...

I must be missing something simple but it looks to me like these two cases
should be the same (can you say De Morgan?):

if (hndshk_to_fpga | inc_ndx | rst_ndx) begin
//do nothing
end
else begin
hndshk_from_motor = 0;
end



if (~hndshk_to_fpga & ~inc_ndx & ~rst_ndx) begin
hndshk_from_motor = 0;
end
else begin
//do nothing
end


Signal hndshk_to_fpga is a 1-bit input. Signals inc_ndx and rst_ndx are
1-bit registers. Example 1 works, example 2 doesn't.

Thanks,
Tom