D
Davy
Guest
Hi all,
There is a SystemVerilog/Verilog code.
What's "continue" in "if" block mean? If I delete "continue", will the
function same? Thanks!
//------------
forever begin
@(posedge clk);
if (reset) begin
... ...
do something;
continue;
end
case(state)
... ...
do something;
... ...
end
//--------------
Best regards,
Davy
There is a SystemVerilog/Verilog code.
What's "continue" in "if" block mean? If I delete "continue", will the
function same? Thanks!
//------------
forever begin
@(posedge clk);
if (reset) begin
... ...
do something;
continue;
end
case(state)
... ...
do something;
... ...
end
//--------------
Best regards,
Davy