Guest
Hi guys,
It's been a while since I messed around with LTSpice but I don't remember ever encountering such a basic problem as this; trying to simulate a cap charging through a resistor and getting a result which shows the cap fully charged right from the get-go! I must be making a really dumb mistake here but I cannot seem to figure out where! Can anyone spot what it is? (I'm ready for this to be seriously embarrassing....)
"ExpressPCB Netlist"
"LTspice IV Version 4.17"
1
0
0
""
""
""
"Part IDs Table"
"C1" "100ľ" ""
"R1" "1000" ""
"V1" "10" ""
"Net Names Table"
"N002" 1
"0" 3
"N001" 5
"Net Connections Table"
1 1 1 2
1 2 1 0
2 1 2 4
2 3 2 0
3 2 2 6
3 3 1 0
It's been a while since I messed around with LTSpice but I don't remember ever encountering such a basic problem as this; trying to simulate a cap charging through a resistor and getting a result which shows the cap fully charged right from the get-go! I must be making a really dumb mistake here but I cannot seem to figure out where! Can anyone spot what it is? (I'm ready for this to be seriously embarrassing....)
"ExpressPCB Netlist"
"LTspice IV Version 4.17"
1
0
0
""
""
""
"Part IDs Table"
"C1" "100ľ" ""
"R1" "1000" ""
"V1" "10" ""
"Net Names Table"
"N002" 1
"0" 3
"N001" 5
"Net Connections Table"
1 1 1 2
1 2 1 0
2 1 2 4
2 3 2 0
3 2 2 6
3 3 1 0