A
afd
Guest
I was reading (with interest), that SystemVerilog 3.1a adds several
'predefined' (i.e. reserved) macros to let a a source-file determine
things about its environment.
But, I don't know if these are 'standard' macros (i.e. are all tools
required
to define them?), or just some inventions of a particular company's
product.
Example:
`SYNTHESIS // defined in Synosys Design_Compiler Verilog-2001
I'd like to know if there is a `SYSTEMVERILOG predefined macro?
For example, I'd like to do something along these lines:
`ifdef SYSTEMVERILOG
// yes, I am in Systemverilog mode
`else
// nope, the host tool doesn't support Systemverilog
`endif
Also, is there a standard-list of these things?
'predefined' (i.e. reserved) macros to let a a source-file determine
things about its environment.
But, I don't know if these are 'standard' macros (i.e. are all tools
required
to define them?), or just some inventions of a particular company's
product.
Example:
`SYNTHESIS // defined in Synosys Design_Compiler Verilog-2001
I'd like to know if there is a `SYSTEMVERILOG predefined macro?
For example, I'd like to do something along these lines:
`ifdef SYSTEMVERILOG
// yes, I am in Systemverilog mode
`else
// nope, the host tool doesn't support Systemverilog
`endif
Also, is there a standard-list of these things?