P
Philipp
Guest
Hello
I have implemented an multiplier in the following way: I always take 4
bits
of my first operand and multiply it with the second operand. So in every
step I generate 4 partial products which have to be added. This sum is
stored in the accumulator. In the next clock cycle I take the next 4
bits,
multiply it with the second operand, sum up the partial products and add
this to my accumulator. This is performed a few times until I have
processed
all the bits of operand one. Then my result is stored in the accu.
My implementation works fine but when I synthesize it I get a lot of
"warnings", can somebody tell me what went wrong here?
Mapping all equations...
Building and optimizing final netlist ...
Register outp_0 equivalent to accu1_8 has been removed
Register outp_1 equivalent to accu1_9 has been removed
Register outp_2 equivalent to accu1_10 has been removed
Register outp_3 equivalent to accu1_11 has been removed
Register outp_4 equivalent to accu1_12 has been removed
Register outp_5 equivalent to accu1_13 has been removed
Register outp_6 equivalent to accu1_14 has been removed
Register outp_7 equivalent to accu1_15 has been removed
Register outp_8 equivalent to accu1_16 has been removed
Register outp_9 equivalent to accu1_17 has been removed
and so on...
The code for accu1 and outp looks the following:
if rst = '1' then
op1 <= (others => '0');
op2 <= (others => '0');
outp <= (others => '0');
accu1 <= (others => '0');
elsif clk'event and clk = '1' then
if load = '1' then
op1 <= inp0;
op2 <= inp1;
end if;
if shift = '1' then
op2 <= op2((2*width-10 downto 0) & (7 downto 0 => '0');
end if;
if acc = '1' then
accu1 <= accu((2*width-1) downto 0) & (7 downto 0 => '0');
outp<= "00" & accu((2*width-3) downto 0);
end if;
end if;
end process;
accu represents always the newest Accumulator value. Hope somebody can
explain me how to get rid of all these warnings
Cheers
Philipp
I have implemented an multiplier in the following way: I always take 4
bits
of my first operand and multiply it with the second operand. So in every
step I generate 4 partial products which have to be added. This sum is
stored in the accumulator. In the next clock cycle I take the next 4
bits,
multiply it with the second operand, sum up the partial products and add
this to my accumulator. This is performed a few times until I have
processed
all the bits of operand one. Then my result is stored in the accu.
My implementation works fine but when I synthesize it I get a lot of
"warnings", can somebody tell me what went wrong here?
Mapping all equations...
Building and optimizing final netlist ...
Register outp_0 equivalent to accu1_8 has been removed
Register outp_1 equivalent to accu1_9 has been removed
Register outp_2 equivalent to accu1_10 has been removed
Register outp_3 equivalent to accu1_11 has been removed
Register outp_4 equivalent to accu1_12 has been removed
Register outp_5 equivalent to accu1_13 has been removed
Register outp_6 equivalent to accu1_14 has been removed
Register outp_7 equivalent to accu1_15 has been removed
Register outp_8 equivalent to accu1_16 has been removed
Register outp_9 equivalent to accu1_17 has been removed
and so on...
The code for accu1 and outp looks the following:
if rst = '1' then
op1 <= (others => '0');
op2 <= (others => '0');
outp <= (others => '0');
accu1 <= (others => '0');
elsif clk'event and clk = '1' then
if load = '1' then
op1 <= inp0;
op2 <= inp1;
end if;
if shift = '1' then
op2 <= op2((2*width-10 downto 0) & (7 downto 0 => '0');
end if;
if acc = '1' then
accu1 <= accu((2*width-1) downto 0) & (7 downto 0 => '0');
outp<= "00" & accu((2*width-3) downto 0);
end if;
end if;
end process;
accu represents always the newest Accumulator value. Hope somebody can
explain me how to get rid of all these warnings
Cheers
Philipp