What use of Python, Perl in FPGA development?

[fl]

Hi,

I often see some FPGA positions requiring Python, Perl. What use of these
scripting language? I know TCL used in FPGA tool chain. I am very curious
about it?

Thanks,

 

[Thomas Stanka]

Hi,
Around the tools (that indeed have usually TCL included) are often a wide variety of additional scripts to help you automate your designflow in several aspects (eg. code generators, make-mechanism, filter tool reports, manage regression tests,.... ).

For these scripts is usually Phyton and Perl required, as TCL is not very compfortable.

regards Thomas

 

[fl]

On Friday, July 4, 2014 10:35:32 PM UTC-4, Aylons Hazzud wrote:

Le vendredi 4 juillet 2014 19:15:14 UTC-3, fl a écrit :

On Friday, July 4, 2014 8:20:34 AM UTC-4, fl wrote:



On Thursday, July 3, 2014 9:20:12 AM UTC-4, Aylons Hazzud wrote:







One example is the hdlmake project[1]: a very nice HDL project manager, build in Python. It allows you to flexibly manage multi-language and multi-plataform projects.































Another example is MyHDL[2], a python-based HDL code generator[2].































[1] http://www.ohwr.org/projects/hdl-make















[2] http://www.myhdl.org/































Le jeudi 3 juillet 2014 08:16:55 UTC-3, Thomas Stanka a écrit :















Hi,































Around the tools (that indeed have usually TCL included) are often a wide variety of additional scripts to help you automate your designflow in several aspects (eg. code generators, make-mechanism, filter tool reports, manage regression tests,.... ).































































For these scripts is usually Phyton and Perl required, as TCL is not very compfortable.































































regards Thomas















Thank you very much. It really looks like an excellent tool.















I am still new to Linux.I download the first (hdlmake-v1.0) from the below 4







files. And put it under ~(Home) directory in Ubuntu 12.04 LTS. I can rename







the full hdlmake-v1.0 to hdlmake (as in its tutorial of the author)?































hdlmake-v1.0 05/05/2013 15:20 37 kB 184







hdlmake-v1.0-isyp 05/05/2013 15:21 40.8 kB 53







hdlmake-v1.0-isyp.tar.gz 05/05/2013 15:20 220.3 kB 62







hdlmake-v1.0.tar.gz 05/05/2013 15:20 100.5 kB 126







On the author's website, he said:







Downloading the compiled executable







For downloading the compiled executable, click here and choose one of the files without extension. Download to a location of choice, and you're almost ready to use it! You can jump directly to the final steps.







He said that "choose one of the files without extension". Is it this one:







hdlmake-v1.0 05/05/2013 15:20 37 kB 184











In which directory do you put it? I am using Ubuntu 12.04.







Thanks,



You may put it wherever it works best for you. When invoking the tool, you just have to make sure to use the full path.



Later, if you want to, you may put the directory in the $PATH environment variable so you won't have to use the full path every time you use the tool. Google how to do it, it is a very common task.

Thank you. I have managed to run the first synthesis with this tool. Great!
In the end, it says that there is an error:

ERROR:Xst:2793 - Top module <led_ctrl_top> specified via the -top switch was not found in any library.

I install Xilinx ISE 14.2 on Ubuntu 12.04 32-bit. Is the tool not compatible,
or the sample design, downloaded from the tool author's website intentionally
having an error? I am still not very clear about the above error message.

Do you see where the "-top" switch? In which library does it search for?


Thanks,




Full message from my running:

robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$ source /opt/Xilinx/14.2/ISE_DS/settings32.sh
.. /opt/Xilinx/14.2/ISE_DS/common/.settings32.sh /opt/Xilinx/14.2/ISE_DS/common
.. /opt/Xilinx/14.2/ISE_DS/EDK/.settings32.sh /opt/Xilinx/14.2/ISE_DS/EDK
.. /opt/Xilinx/14.2/ISE_DS/common/CodeSourcery/.settings32.sh /opt/Xilinx
/14.2/ISE_DS/common/CodeSourcery
.. /opt/Xilinx/14.2/ISE_DS/PlanAhead/.settings32.sh /opt/Xilinx/14.2/ISE_DS
/PlanAhead
.. /opt/Xilinx/14.2/ISE_DS/ISE/.settings32.sh /opt/Xilinx/14.2/ISE_DS/ISE
robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$ env
SSH_AGENT_PID=2021
GPG_AGENT_INFO=/tmp/keyring-tFgbsf/gpg:0:1
XILINX_DSP=/opt/Xilinx/14.2/ISE_DS/ISE
TERM=xterm
SHELL=/bin/bash
XDG_SESSION_COOKIE=32b521a8b574c9de6facec5a00000008-1404558998.97504-1715864184
WINDOWID=56623110
OLDPWD=/home/robert/pyprj/fmc-adc-100m14b4cha/play
GNOME_KEYRING_CONTROL=/tmp/keyring-tFgbsf
USER=robert
LD_LIBRARY_PATH=/opt/Xilinx/14.2/ISE_DS/ISE/lib/lin:/opt/Xilinx/14.2/ISE_DS
/EDK/lib/lin:/opt/Xilinx/14.2/ISE_DS/common/lib/lin
LS_COLORS=rs=0:di=01;34:ln=01;36:mh=00i=40;33:so=01;35:do=01;35:bd=40;
33;01:cd=40;33;01r=40;31;01:su=37;41:sg=30;43:ca=30;41:tw=30;42w=34;
42:st=37;44:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;
31:*.lzma=01;31:*.tlz=01;31:*.txz=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.dz=01;
31:*.gz=01;31:*.lz=01;31:*.xz=01;31:*.bz2=01;31:*.bz=01;31:*.tbz=01;
31:*.tbz2=01;31:*.tz=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.war=01;
31:*.ear=01;31:*.sar=01;31:*.rar=01;31:*.ace=01;31:*.zoo=01;31:*.cpio=01;
31:*.7z=01;31:*.rz=01;31:*.jpg=01;35:*.jpeg=01;35:*.gif=01;35:*.bmp=01;
35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;
35:*.tif=01;35:*.tiff=01;35:*.png=01;35:*.svg=01;35:*.svgz=01;35:*.mng=01;
35:*.pcx=01;35:*.mov=01;35:*.mpg=01;35:*.mpeg=01;35:*.m2v=01;35:*..mkv=01;
35:*.webm=01;35:*.ogm=01;35:*.mp4=01;35:*.m4v=01;35:*.mp4v=01;35:*.vob=01;
35:*.qt=01;35:*.nuv=01;35:*.wmv=01;35:*.asf=01;35:*.rm=01;35:*.rmvb=01;
35:*.flc=01;35:*.avi=01;35:*.fli=01;35:*.flv=01;35:*.gl=01;35:*.dl=01;
35:*.xcf=01;35:*.xwd=01;35:*.yuv=01;35:*.cgm=01;35:*.emf=01;35:*.axv=01;
35:*.anx=01;35:*.ogv=01;35:*.ogx=01;35:*.aac=00;36:*.au=00;36:*.flac=00;
36:*.mid=00;36:*.midi=00;36:*.mka=00;36:*.mp3=00;36:*.mpc=00;36:*..ogg=00;
36:*.ra=00;36:*.wav=00;36:*.axa=00;36:*.oga=00;36:*.spx=00;36:*.xspf=00;36:
LIBGL_DRIVERS_PATH=/usr/lib/fglrx/dri:/usr/lib/i386-linux-gnu/dri:/usr/lib/dri
XDG_SESSION_PATH=/org/freedesktop/DisplayManager/Session0
XILINX_EDK=/opt/Xilinx/14.2/ISE_DS/EDK
XDG_SEAT_PATH=/org/freedesktop/DisplayManager/Seat0
SSH_AUTH_SOCK=/tmp/keyring-tFgbsf/ssh
SESSION_MANAGER=local/MS-7696/tmp/.ICE-unix/1984,unix/MS-7696:/tmp/.ICE-
unix/1984
DEFAULTS_PATH=/usr/share/gconf/ubuntu.default.path
XDG_CONFIG_DIRS=/etc/xdg/xdg-ubuntu:/etc/xdg
PATH=/opt/Xilinx/14.2/ISE_DS/ISE/bin/lin:/opt/Xilinx/14.2/ISE_DS/ISE/sysgen
/util:/opt/Xilinx/14.2/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.2/ISE_DS/EDK/bin
/lin:/opt/Xilinx/14.2/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.2/ISE_DS
/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.2/ISE_DS/EDK/gnu/arm/lin/bin:/opt
/Xilinx/14.2/ISE_DS/common/bin/lin:/usr/lib/lightdm/lightdm:/usr/local/sbin:
/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games
DESKTOP_SESSION=ubuntu
PWD=/home/robert/pyprj/fmc-adc-100m14b4cha/play/syn
GNOME_KEYRING_PID=1973
LANG=en_CA.UTF-8
MANDATORY_PATH=/usr/share/gconf/ubuntu.mandatory.path
QMAKESPEC=/home/robert/ti-sdk-am335x-evm-06.00.00.00/linux-devkit/arm-arago-linux-gnueabi/usr/share/qtopia/mkspecs/linux-g++
UBUNTU_MENUPROXY=libappmenu.so
COMPIZ_CONFIG_PROFILE=ubuntu
GDMSESSION=ubuntu
__KMP_REGISTERED_LIB_2052=0xb5fb5394-cafefce3-libiomp5.a
SHLVL=1
HOME=/home/robert
LANGUAGE=en_CA:en
GNOME_DESKTOP_SESSION_ID=this-is-deprecated
LOGNAME=robert
XDG_DATA_DIRS=/usr/share/ubuntu:/usr/share/gnome:/usr/local/share/:/usr/share/
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-
Zr40Ve1bAV,guid=a407da5a3fa1e15c9f9840da0000003b
LESSOPEN=| /usr/bin/lesspipe %s
DISPLAY=:0
XILINX_PLANAHEAD=/opt/Xilinx/14.2/ISE_DS/PlanAhead
XDG_CURRENT_DESKTOP=Unity
LESSCLOSE=/usr/bin/lesspipe %s %s
XILINX=/opt/Xilinx/14.2/ISE_DS/ISE
COLORTERM=gnome-terminal
XAUTHORITY=/home/robert/.Xauthority
_=/usr/bin/env
robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$ ./hdlmake-v1.0
INFO: Running automatic flow
INFO: Generating/updating ISE project
INFO: Generating makefile for local synthesis.
WARNING: Connection data is not given. Accessing environmental variables in the
makefile
INFO: Generating makefile for remote synthesis.
robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$ ls
hdlmake-v1.0 led_ctrl.ucf led_ctrl.xise Makefile Manefest.py~ Manifest..py
run.tcl
robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$ ls -al
total 88
drwxrwxr-x 2 robert robert 4096 Jul 5 08:40 .
drwxrwxr-x 7 robert robert 4096 Jul 5 08:03 ..
-rwx--x--x 1 robert robert 37848 Jul 4 06:46 hdlmake-v1.0
-rw-rw-r-- 1 robert robert 22270 Jul 4 20:59 led_ctrl.ucf
-rw-rw-r-- 1 robert robert 2095 Jul 5 08:40 led_ctrl.xise
-rw-rw-r-- 1 robert robert 2702 Jul 5 08:40 Makefile
-rw-rw-r-- 1 robert robert 0 Jul 5 08:33 Manefest.py~
-rw-rw-r-- 1 robert robert 236 Jul 5 08:33 Manifest.py
-rw-rw-r-- 1 robert robert 84 Jul 5 08:40 run.tcl
robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$ make
echo "project open led_ctrl.xise" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/robert/pyprj/fmc-adc-100m14b4cha/play/syn/led_ctrl_top.xst" -ofn "/home/robert/pyprj/fmc-adc-100m14b4cha/play/syn/led_ctrl_top.syr"
Reading design: led_ctrl_top.prj

========================================================================* HDL Parsing *
========================================================================Parsing VHDL file "/home/robert/pyprj/fmc-adc-100m14b4cha/play/hdl/design
/led_ctrl.vhd" into library work
Parsing entity <led_ctrl>.
Parsing architecture <behavioral> of entity <led_ctrl>.
Parsing VHDL file "/home/robert/pyprj/fmc-adc-100m14b4cha/play/hdl/design
/irq_controller_regs.vhd" into library work
Parsing entity <irq_controller_regs>.
Parsing architecture <syn> of entity <irq_controller_regs>.
Parsing VHDL file "/home/robert/pyprj/fmc-adc-100m14b4cha/play/hdl/design
/irq_controller.vhd" into library work
Parsing entity <irq_controller>.
Parsing architecture <rtl> of entity <irq_controller>.
Parsing VHDL file "/home/robert/pyprj/fmc-adc-100m14b4cha/play/hdl/design
/addr_dec.vhd" into library work
Parsing entity <addr_dec>.
Parsing architecture <behavioral> of entity <addr_dec>.

========================================================================* HDL Elaboration *
========================================================================ERROR:Xst:2793 - Top module <led_ctrl_top> specified via the -top switch was
not found in any library.
-->


Total memory usage is 97520 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)


Process "Synthesize - XST" failed
INFO:TclTasksC:1850 - process run : Generate Programming File is done.
robert@MS-7696:~/pyprj/fmc-adc-100m14b4cha/play/syn$

 

[fl]

On Thursday, July 3, 2014 9:20:12 AM UTC-4, Aylons Hazzud wrote:

: a very nice HDL project manager, build in Python. It allows you to flexibly manage multi-language and multi-plataform projects.



Another example is MyHDL[2], a python-based HDL code generator[2].



[1] http://www.ohwr.org/projects/hdl-make

[2] http://www.myhdl.org/



Le jeudi 3 juillet 2014 08:16:55 UTC-3, Thomas Stanka a écrit :

Hi,



Around the tools (that indeed have usually TCL included) are often a wide variety of additional scripts to help you automate your designflow in several aspects (eg. code generators, make-mechanism, filter tool reports, manage regression tests,.... ).







For these scripts is usually Phyton and Perl required, as TCL is not very compfortable.







regards Thomas

Hi,
Finally, it passes Manifest.py. When I run synthesis with make utility, it has
such errors (see below for complete message please):

ERRORrojectMgmt - The software version (13) is older than the version saved in
the project file (14).

I do not know which file it says. Could you help me?

Thanks,



...............................................................
Jeff@Jeff-PC ~/fmc-adc-100m14b4cha/play/syn
$ ./hdlmake-v1.0
INFO: Running automatic flow
INFO: Generating/updating ISE project
INFO: Generating makefile for local synthesis.
WARNING: Connection data is not given. Accessing environmental variables in the makefile
INFO: Generating makefile for remote synthesis.

Jeff@Jeff-PC ~/fmc-adc-100m14b4cha/play/syn
$ make
echo "project open led_ctrl.xise" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
ERRORrojectMgmt - The software version (13) is older than the version saved in
the project file (14).
Opening newer project with older software releases is not supported.
ERRORrojectMgmt - The software version (13) is older than the version saved in
the project file (14).
Opening newer project with older software releases is not supported.
ERROR:TclTasksCroject_085: Error opening specified project "C:/cygwin64/home/Jeff/fmc-adc-100m14b4cha/play/syn/led_ctrl.xise": ERROR:TclTasksC:tcl_project_mgr_007 - Internal error. Can not open "C:\cygwin64\home\Jeff\fmc-adc-100m14b4cha\play\syn\led_ctrl.xise".
..
while executing
"project open led_ctrl.xise"
(file "run.tcl" line 1)
Makefile:11: recipe for target 'local' failed
make: *** [local] Error 1

 

[alb]

Hi Hazzud,

Aylons Hazzud <aylons@gmail.com> wrote:

: a very nice HDL project
manager, build in Python. It allows you to flexibly manage
multi-language and multi-plataform projects.

IMO hdlmake fails in being a 'simple' makefile generation tool, since
it added the complexity of the VCS management and remote synthesis
features which IMO are out of the scope for a 'make' utility (and can
be simply handled separately).

To give an example I installed hdlmake to give it a go and wanted to
start with one of the examples provided with the documentation and
BANG, I was cloning a ~2GB git repository to test an example!

A 'make' tool resolves dependencies, that's all it does. I use vmk to
build my dependencies and I do not ask more to a 'makefile generator'.
The Makefile has hooks that you can use to run whatever other tool or
script you can imagine and is not bound to any X vendor.

There are only two shortcoming of vmk:

1. the library management is not straight forward and I do believe the
author did have another utility to fill the gap (IIRC is called lmk).
While this is a bit of a pity is certainly not a show stopper for using
it.

2. supports only vhdl-93, which is a bit disappointing especially for
testbenches which I tipically write leveraging the new features of
vhdl-2008.

I'm not aware which language standard hdlmake is supporting, at least
I didn't find it in the documentation.

Al