What type of shift does << represent ??

[Daku]

Could some Verilog guru please clarify this a
bit ? What type of shift does &lt;&lt; represent ?
Is it a circular shift (pushed out bits re-inserted
at the other end) or ordinary shift (pushed out
bits replaced by zeros ? Any hints, suggestions
would be helpful. Thanks in advance for your
help.

 

[Gabor]

Daku wrote:

Could some Verilog guru please clarify this a
bit ? What type of shift does &lt;&lt; represent ?
Is it a circular shift (pushed out bits re-inserted
at the other end) or ordinary shift (pushed out
bits replaced by zeros ? Any hints, suggestions
would be helpful. Thanks in advance for your
help.

Not exactly a guru question. &lt;&lt; is a logical shift
left, which turns out to be the same as &lt;&lt;&lt; which
is the arithmetic shift left. In both cases, zero
shifts in from the right.

There is a difference between &gt;&gt; and &gt;&gt;&gt; for signed
operands, but not between &lt;&lt; and &lt;&lt;&lt;. For signed
operands, the arithmetic shift right will replicate
the sign bit as it shifts, while all other right
shifts will shift in a zero.

If you want a "circular shift" you need to explicitly
code bit wrap. This is usually done with concatenation
rather than using the shift operator, but you could also
do it with a left shift ORed with the MSB like:

reg [WIDTH-1:0] foo;
.. . .
foo &lt;= (foo &lt;&lt; 1) | foo[WIDTH-1];

-- Gabor