What time to use Clocking Block in SystemVerilog?

[Davy]

Hi,

I found in some SystemVerilog examples, people like to add Clocking
Block to driver and monitor. While some other SV examples only use
modport (don't use Clocking Block).

So I am confused with it.
1. Is it recommendation to use Clocking Block?
2. Shall I only use it in testbench component like driver and monitor
(shall I use it in responder)?


Best regards,
Davy