What the advantages and disadvantages between distributed ar

[fl]

Hi,

For a filter implementation in FPGA/ASIC, there are two efficient architectures for the MAC. One is distributed arithmetic, while the other is serial-parallel multiplication based. I know that DA normally is for one of the multiplicant is constant. The serial-parallel mulication has no such requirement. When one of the multiplicant is constant, it can save some logic gates indeed. Both methods process one bit with one clock cycle. What the differences are for these two architectures?

Thanks.

 

[Tim Wescott]

On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote:

Hi,

For a filter implementation in FPGA/ASIC, there are two efficient
architectures for the MAC. One is distributed arithmetic, while the
other is serial-parallel multiplication based. I know that DA normally
is for one of the multiplicant is constant. The serial-parallel
mulication has no such requirement. When one of the multiplicant is
constant, it can save some logic gates indeed. Both methods process one
bit with one clock cycle. What the differences are for these two
architectures?

Thanks.

Define "efficient". Operations per clock? Number of gates? Shortness
of pipeline? Joules per operation?

To my knowledge, most FPGAs these days come with built-in, hard-coded MAC
units (at least, you can't seem to swing a cat inside a Xilinx FPGA
without hitting one). So, by many definitions, using one is "most
efficient" if you have such an FPGA.

While I freely admit that I don't have the knowledge base to answer your
question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I strongly
suspect that the real answer is that you need to investigate each one,
and decide which best matches _your_ idea of "efficient".

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

 

[Les Cargill]

Tim Wescott wrote:

On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote:

Hi,

For a filter implementation in FPGA/ASIC, there are two efficient
architectures for the MAC. One is distributed arithmetic, while the
other is serial-parallel multiplication based. I know that DA normally
is for one of the multiplicant is constant. The serial-parallel
mulication has no such requirement. When one of the multiplicant is
constant, it can save some logic gates indeed. Both methods process one
bit with one clock cycle. What the differences are for these two
architectures?

Thanks.

Define "efficient". Operations per clock? Number of gates? Shortness
of pipeline? Joules per operation?

To my knowledge, most FPGAs these days come with built-in, hard-coded MAC
units (at least, you can't seem to swing a cat inside a Xilinx FPGA
without hitting one). So, by many definitions, using one is "most
efficient" if you have such an FPGA.

While I freely admit that I don't have the knowledge base to answer your
question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I strongly
suspect that the real answer is that you need to investigate each one,
and decide which best matches _your_ idea of "efficient".

All the fun part is done in the magjack anyway. An Ethernet MAC is
mostly tedium.

--
Les Cargill

 

[Tim Wescott]

On Sun, 11 Nov 2012 17:13:20 -0600, Les Cargill wrote:

Tim Wescott wrote:
On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote:

Hi,

For a filter implementation in FPGA/ASIC, there are two efficient
architectures for the MAC. One is distributed arithmetic, while the
other is serial-parallel multiplication based. I know that DA normally
is for one of the multiplicant is constant. The serial-parallel
mulication has no such requirement. When one of the multiplicant is
constant, it can save some logic gates indeed. Both methods process
one bit with one clock cycle. What the differences are for these two
architectures?

Thanks.

Define "efficient". Operations per clock? Number of gates? Shortness
of pipeline? Joules per operation?

To my knowledge, most FPGAs these days come with built-in, hard-coded
MAC units (at least, you can't seem to swing a cat inside a Xilinx FPGA
without hitting one). So, by many definitions, using one is "most
efficient" if you have such an FPGA.

While I freely admit that I don't have the knowledge base to answer
your question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I
strongly suspect that the real answer is that you need to investigate
each one, and decide which best matches _your_ idea of "efficient".



All the fun part is done in the magjack anyway. An Ethernet MAC is
mostly tedium.

I hope you realize that I meant "multiply and accumulate", not "media
access" or whatever MAC means to Ethernet. At any rate, count my leg as
pulled.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

 

[Les Cargill]

Tim Wescott wrote:

On Sun, 11 Nov 2012 17:13:20 -0600, Les Cargill wrote:

Tim Wescott wrote:
On Sat, 10 Nov 2012 16:48:35 -0800, fl wrote:

Hi,

For a filter implementation in FPGA/ASIC, there are two efficient
architectures for the MAC. One is distributed arithmetic, while the
other is serial-parallel multiplication based. I know that DA normally
is for one of the multiplicant is constant. The serial-parallel
mulication has no such requirement. When one of the multiplicant is
constant, it can save some logic gates indeed. Both methods process
one bit with one clock cycle. What the differences are for these two
architectures?

Thanks.

Define "efficient". Operations per clock? Number of gates? Shortness
of pipeline? Joules per operation?

To my knowledge, most FPGAs these days come with built-in, hard-coded
MAC units (at least, you can't seem to swing a cat inside a Xilinx FPGA
without hitting one). So, by many definitions, using one is "most
efficient" if you have such an FPGA.

While I freely admit that I don't have the knowledge base to answer
your question vis-a-vis ASICs, or FPGAs lacking hard-coded MAC, I
strongly suspect that the real answer is that you need to investigate
each one, and decide which best matches _your_ idea of "efficient".



All the fun part is done in the magjack anyway. An Ethernet MAC is
mostly tedium.

I hope you realize that I meant "multiply and accumulate", not "media
access" or whatever MAC means to Ethernet. At any rate, count my leg as
pulled.

I went halfway through the thread before I realized it *was* a
"Multiply and Acucmulate", which was the inspiration for the joke.

We're running out of TLAs.

--
Les Cargill