what must be associated in verilog file with LEF when import

[Echo]

Hello!
I import the verilog file netlist and the LEF of abstract generator
into the SOC ENCOUNTER,but after floorplan,there are some triangle
pins on the main window.It seems quite strange!
There is somthing must be parallelism between the netlist and the
LEF?I only known the name of macro in LEF must the same as verilog's
module,and the pins of macro are parallelism to the pins of standard
cell.
Is other constraint?
Thanks!