what is wrong with this state machine?

V

Verictor

Guest
Hi,

I am looking the following state machine. It seems no problem on
simulation. But when synthesize it, the problem turns out that one of
the input nets (input b) can't connect to any net (no warning on input
a though).

So how to assign inputs (a,b, and c in the example) to drive output
(z) and internal registers (z1 and z2)? The internal registers are
needed.

module fsm(clock, reset, a, b, c, z);
input clock, reset;
input a, b, c;
output z;
reg z;

reg z1, z2;

parameter s0 = 1'b0,
s1 = 1'b1;

reg state, next;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= s0;
end else begin
state <= next;
end
end

always @(*) begin
next = 1'bx;
z = 1'b0;
z1 = 1'b0;
z2 = 1'b0;
case(state)
s0: if (a&b) begin
next = s1;
z1 = c;
z2 = a;
end

s1: if(c) begin
next = s0;
z = a;
z1 = 1'b1;
z2 = b;
end
endcase
end

endmodule
 
After making some changes as shown following, the two registers z1 and
z2 are not being instatiated but only state is instantiated in
synthesis. Why is that?

module fsm(clock, reset, a, b, c, z);
input clock, reset;
input a, b, c;
output z;
reg z;

reg z1, z2;
reg next1, next2;

parameter s0 = 1'b0,
s1 = 1'b1;

reg state, next;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= s0;
z1 <= s1;
z2 <= s1;
end else begin
state <= next;
z1 <= next1;
z2 <= next2;
end
end

always @(*) begin
next = 1'bx;
z = 1'b0;
next1 = 1'bx;
next2 = 1'bx;
case(state)
s0: if (a&b) begin
next = s1;
next1 = s0;
next2 = s1;
end

s1: if(c) begin
next = s0;
z = a;
next1 = 1'b1;
next2 = s1;
end
endcase
end

endmodule
 
On Mar 27, 1:21 pm, "Verictor" <stehu...@gmail.com> wrote:
After making some changes as shown following, the two registers z1 and
z2 are not being instatiated but only state is instantiated in
synthesis. Why is that?

module fsm(clock, reset, a, b, c, z);
input clock, reset;
input a, b, c;
output z;
reg z;

reg z1, z2;
reg next1, next2;

parameter s0 = 1'b0,
s1 = 1'b1;

reg state, next;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= s0;
z1 <= s1;
z2 <= s1;
end else begin
state <= next;
z1 <= next1;
z2 <= next2;
end
end

always @(*) begin
next = 1'bx;
z = 1'b0;
next1 = 1'bx;
next2 = 1'bx;
case(state)
s0: if (a&b) begin
next = s1;
next1 = s0;
next2 = s1;
end

s1: if(c) begin
next = s0;
z = a;
next1 = 1'b1;
next2 = s1;
end
endcase
end

endmodule
Click to expand...
I just verified that Synopsys won't instatiate flipflops for
intermediate declared regs except that the regs are for outputs. Is
there a way to instantiate intermediate regs in the above state
machine?
 
On 28 Mar, 01:57, "Verictor" <stehu...@gmail.com> wrote:
On Mar 27, 1:21 pm, "Verictor" <stehu...@gmail.com> wrote:



After making some changes as shown following, the two registers z1 and
z2 are not being instatiated but only state is instantiated in
synthesis. Why is that?

module fsm(clock, reset, a, b, c, z);
input clock, reset;
input a, b, c;
output z;
reg z;

reg z1, z2;
reg next1, next2;

parameter s0 = 1'b0,
s1 = 1'b1;

reg state, next;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= s0;
z1 <= s1;
z2 <= s1;
end else begin
state <= next;
z1 <= next1;
z2 <= next2;
end
end

always @(*) begin
next = 1'bx;
z = 1'b0;
next1 = 1'bx;
next2 = 1'bx;
case(state)
s0: if (a&b) begin
next = s1;
next1 = s0;
next2 = s1;
end

s1: if(c) begin
next = s0;
z = a;
next1 = 1'b1;
next2 = s1;
end
endcase
end

endmodule

I just verified that Synopsys won't instatiate flipflops for
intermediate declared regs except that the regs are for outputs. Is
there a way to instantiate intermediate regs in the above state
machine?
Click to expand...

z1 and z2 are not synthesized because they are never used.
You said you need those registers, but you never use them in any
statement.
 
On Mar 28, 2:25 am, "Paolo Lombardi" <paolo.lomba...@gmail.com> wrote:
On 28 Mar, 01:57, "Verictor" <stehu...@gmail.com> wrote:





On Mar 27, 1:21 pm, "Verictor" <stehu...@gmail.com> wrote:

After making some changes as shown following, the two registers z1 and
z2 are not being instatiated but only state is instantiated in
synthesis. Why is that?

module fsm(clock, reset, a, b, c, z);
input clock, reset;
input a, b, c;
output z;
reg z;

reg z1, z2;
reg next1, next2;

parameter s0 = 1'b0,
s1 = 1'b1;

reg state, next;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= s0;
z1 <= s1;
z2 <= s1;
end else begin
state <= next;
z1 <= next1;
z2 <= next2;
end
end

always @(*) begin
next = 1'bx;
z = 1'b0;
next1 = 1'bx;
next2 = 1'bx;
case(state)
s0: if (a&b) begin
next = s1;
next1 = s0;
next2 = s1;
end

s1: if(c) begin
next = s0;
z = a;
next1 = 1'b1;
next2 = s1;
end
endcase
end

endmodule

I just verified that Synopsys won't instatiate flipflops for
intermediate declared regs except that the regs are for outputs. Is
there a way to instantiate intermediate regs in the above state
machine?

z1 and z2 are not synthesized because they are never used.
You said you need those registers, but you never use them in any
statement.- Hide quoted text -

- Show quoted text -
Click to expand...
Right, there are not used in the above simplified example. So if I
modify a bit the above module

wire y;

assign y = z1;

Then z1 will be instantiated.

Thanks a lot
 
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