What is tut1 for here?

R

Robert Willy

Guest
Hi,
I am new to verilog. I don't find an answer for 'tut1' in the testbench.

tutorial tut1(.led(leds),.swt(switches));


Could you help me out?


thanks,


,,,,,,,,,,,,,,,,,,,,,,,,

module tutorial_tb(

);

reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;

integer i;

tutorial tut1(.led(leds),.swt(switches));

function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction

initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end

endmodule
............

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: tutorial
//////////////////////////////////////////////////////////////////////////////////


module tutorial(
input [7:0] swt,
output [7:0] led
);

assign led[0] = ~swt[0];
assign led[1] = swt[1] & ~swt[2];
assign led[3] = swt[2] & swt[3];
assign led[2] = led[1] | led[3];

assign led[7:4] = swt[7:4];

endmodule
 
On Friday, 5/5/2017 3:48 PM, Robert Willy wrote:
Hi,
I am new to verilog. I don't find an answer for 'tut1' in the testbench.

tutorial tut1(.led(leds),.swt(switches));


Could you help me out?


thanks,


,,,,,,,,,,,,,,,,,,,,,,,,

module tutorial_tb(

);

reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;

integer i;

tutorial tut1(.led(leds),.swt(switches));

function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction

initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end

endmodule
...........

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: tutorial
//////////////////////////////////////////////////////////////////////////////////


module tutorial(
input [7:0] swt,
output [7:0] led
);

assign led[0] = ~swt[0];
assign led[1] = swt[1] & ~swt[2];
assign led[3] = swt[2] & swt[3];
assign led[2] = led[1] | led[3];

assign led[7:4] = swt[7:4];

endmodule
Click to expand...

tut1 is just the instance name. In Verilog, when you instantiate a
module you are required to assign it a unique instance name. This
is used for hierarchical names so your test bench can access code
outside its own context. In your case, the "tutorial" module has
no internal signals defined, so hierarchical names are not very
useful. However imagine that it had some internal signal like:

reg [3:0] foo; // this would be inside tutorial module

Then your testbench could access that register like:

$display ("foo equals %d", tut1.foo); // this would be in tutorial_tb

It's common in testbench code to use a name like UUT
(unit under test) as the instance name for the module
being tested. However the instance name has no special
meaning. It just needs to be unique and not a reserved
word.

--
Gabor
 
On Friday, May 5, 2017 at 6:09:17 PM UTC-4, Gabor wrote:
On Friday, 5/5/2017 3:48 PM, Robert Willy wrote:
Hi,
I am new to verilog. I don't find an answer for 'tut1' in the testbench.

tutorial tut1(.led(leds),.swt(switches));


Could you help me out?


thanks,


,,,,,,,,,,,,,,,,,,,,,,,,

module tutorial_tb(

);

reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;

integer i;

tutorial tut1(.led(leds),.swt(switches));

function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction

initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end

endmodule
...........

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: tutorial
//////////////////////////////////////////////////////////////////////////////////


module tutorial(
input [7:0] swt,
output [7:0] led
);

assign led[0] = ~swt[0];
assign led[1] = swt[1] & ~swt[2];
assign led[3] = swt[2] & swt[3];
assign led[2] = led[1] | led[3];

assign led[7:4] = swt[7:4];

endmodule


tut1 is just the instance name. In Verilog, when you instantiate a
module you are required to assign it a unique instance name. This
is used for hierarchical names so your test bench can access code
outside its own context. In your case, the "tutorial" module has
no internal signals defined, so hierarchical names are not very
useful. However imagine that it had some internal signal like:

reg [3:0] foo; // this would be inside tutorial module

Then your testbench could access that register like:

$display ("foo equals %d", tut1.foo); // this would be in tutorial_tb

It's common in testbench code to use a name like UUT
(unit under test) as the instance name for the module
being tested. However the instance name has no special
meaning. It just needs to be unique and not a reserved
word.

--
Gabor
Click to expand...

Thank you so much. My previous question was too simple to post. Sorry about
it.
Now this one looks very strange to me. I find that '@' means waiting for
something. What is '*' here? It is the same wild character in a command
console?

..................
always @(*) begin
ctr_d = ctr_q + 1'b1;

if (compare > ctr_q)
pwm_d = 1'b1;
else
pwm_d = 1'b0;
end
 
On 5/5/2017 8:42 PM, Robert Willy wrote:
On Friday, May 5, 2017 at 6:09:17 PM UTC-4, Gabor wrote:
On Friday, 5/5/2017 3:48 PM, Robert Willy wrote:
Hi,
I am new to verilog. I don't find an answer for 'tut1' in the testbench.

tutorial tut1(.led(leds),.swt(switches));


Could you help me out?


thanks,


,,,,,,,,,,,,,,,,,,,,,,,,

module tutorial_tb(

);

reg [7:0] switches;
wire [7:0] leds;
reg [7:0] e_led;

integer i;

tutorial tut1(.led(leds),.swt(switches));

function [7:0] expected_led;
input [7:0] swt;
begin
expected_led[0] = ~swt[0];
expected_led[1] = swt[1] & ~swt[2];
expected_led[3] = swt[2] & swt[3];
expected_led[2] = expected_led[1] | expected_led[3];
expected_led[7:4] = swt[7:4];
end
endfunction

initial
begin
for (i=0; i < 255; i=i+2)
begin
#50 switches=i;
#10 e_led = expected_led(switches);
if(leds == e_led)
$display("LED output matched at", $time);
else
$display("LED output mis-matched at ",$time,": expected: %b, actual: %b", e_led, leds);
end
end

endmodule
...........

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: tutorial
//////////////////////////////////////////////////////////////////////////////////


module tutorial(
input [7:0] swt,
output [7:0] led
);

assign led[0] = ~swt[0];
assign led[1] = swt[1] & ~swt[2];
assign led[3] = swt[2] & swt[3];
assign led[2] = led[1] | led[3];

assign led[7:4] = swt[7:4];

endmodule


tut1 is just the instance name. In Verilog, when you instantiate a
module you are required to assign it a unique instance name. This
is used for hierarchical names so your test bench can access code
outside its own context. In your case, the "tutorial" module has
no internal signals defined, so hierarchical names are not very
useful. However imagine that it had some internal signal like:

reg [3:0] foo; // this would be inside tutorial module

Then your testbench could access that register like:

$display ("foo equals %d", tut1.foo); // this would be in tutorial_tb

It's common in testbench code to use a name like UUT
(unit under test) as the instance name for the module
being tested. However the instance name has no special
meaning. It just needs to be unique and not a reserved
word.

--
Gabor

Thank you so much. My previous question was too simple to post. Sorry about
it.
Now this one looks very strange to me. I find that '@' means waiting for
something. What is '*' here? It is the same wild character in a command
console?

..................
always @(*) begin
ctr_d = ctr_q + 1'b1;

if (compare > ctr_q)
pwm_d = 1'b1;
else
pwm_d = 1'b0;
end
Click to expand...

Don't you have a text book for this? How about trying a google search?
These are easy questions that you should be able to answer by reading
any of the many materials available.

http://stackoverflow.com/questions/8865877/verilog-always-begin-and-end-evaluation

--

Rick C
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top