Guest
I'm trying figure out the sample and hold time of an ADC. In other
words, not the sample rate, but how fast the sample and hold works.
I'm comparing two chips.
Chip #1
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,P11972,D8597
tAP (Sample-and-hold acquisition delay time) is 0 ns.
tJitter (Sample-and-hold acquisition delay time jitter) is 0.2 psRMS.
Chip #2
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,P1644,D2894
Advertises a 250MHz Internal Sample-and-hold
tAP (Sample-and-hold acquisition delay time) is 3 ns.
tJitter (Sample-and-hold acquisition delay time jitter) is 5 psRMS.
Could someone please explain what this means? I didn't see any sample
and hold frequency for Chip #1. I can understand why ADC need a sample
and hold because the signal is most likely changing. So the ADC wants
to work on a non-changing voltage. Chip #2 explanation of the sample
and hold seems easy to understand-- 250MHz. If we associated a
frequency to chip #1 then what would that be?
Thanks,
Paul
words, not the sample rate, but how fast the sample and hold works.
I'm comparing two chips.
Chip #1
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,P11972,D8597
tAP (Sample-and-hold acquisition delay time) is 0 ns.
tJitter (Sample-and-hold acquisition delay time jitter) is 0.2 psRMS.
Chip #2
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,P1644,D2894
Advertises a 250MHz Internal Sample-and-hold
tAP (Sample-and-hold acquisition delay time) is 3 ns.
tJitter (Sample-and-hold acquisition delay time jitter) is 5 psRMS.
Could someone please explain what this means? I didn't see any sample
and hold frequency for Chip #1. I can understand why ADC need a sample
and hold because the signal is most likely changing. So the ADC wants
to work on a non-changing voltage. Chip #2 explanation of the sample
and hold seems easy to understand-- 250MHz. If we associated a
frequency to chip #1 then what would that be?
Thanks,
Paul