What is this ASMBL thing from Xilinx?

[Rahul Khanna]

Xilinx seems to have launched a new architecture - ASMBL. There is no
information except a news article. Can we have more info??? Is anyone
from Xilinx Listening????

 

[John Adair]

I don't think there will be any more public domain data for a while. Parts
are similarly unlikely be around for a few months. If you have a serious
design interest then the best approach will be to approach your FAE who may
able to arrange early access via a NDA.

We are still coming terms with the new family ourselves. But the main
details that have been released indicate that their is a modular fabric.
With this fabric Xilinx can produce multiple variants of a given die size
allowing them target particular market sector needs.


John Adair
Enterpoint Ltd.
Xilinx Xperts Partners

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


"Rahul Khanna" <rahulkh888@yahoo.com> wrote in message
news:7897cd1e.0312161940.17e89bcb@posting.google.com...

Xilinx seems to have launched a new architecture - ASMBL. There is no
information except a news article. Can we have more info??? Is anyone
from Xilinx Listening????

 

[Jim Granville]

Rahul Khanna wrote:

Xilinx seems to have launched a new architecture - ASMBL. There is no
information except a news article. Can we have more info??? Is anyone
from Xilinx Listening????

There was an earlier thread on this.
I did find the PDF on the Xilinx web site that was a little clearer,
as it had (virtual?) die photos.
( Web info has gone Engineering -> Marketing -> web Publishing, whilst
the PDF has only had Engineering -> Marketing 'content removal'
Info so far shows some good mechanical ideas for lowering the cost
of creating new die mixtures.
The Real Test will be the Volumes/NRE cost numbers, but they are
flag waving mainly at the ASIC customers, and remember Xilinx do not
have a HardCopy flow like Altera.
One aspect of the Xilinx approach, is it allows Hard IP, AND
keeps _some_ FPGA fabric - again, nice if you are big enough to
'get the stripes you want spun'
-jg

 

[Peter Alfke]

Somebody from Xilinx is always listening
The purpose of that press release was to create interest, exitement, and
suspense.
Obviously, it did succeed.
I know lots of technical details, but I cannot tell. For good reasons,
Marketing is in charge of releasing information. Please be patient, "you
will be richly rewarded"!

It is still an FPGA, to be configured by the customer. We are not
entering the ASIC business... ( We just want to capture more of its $$$s
)

Peter Alfke

Rahul Khanna wrote:

Xilinx seems to have launched a new architecture - ASMBL. There is no
information except a news article. Can we have more info??? Is anyone
from Xilinx Listening????

 

[john jakson]

Peter Alfke <Peter.Alfke@xilinx.com> wrote in message news:<3FE0DA9D.A27E7E4F@xilinx.com>...

Somebody from Xilinx is always listening
The purpose of that press release was to create interest, exitement, and
suspense.
Obviously, it did succeed.
I know lots of technical details, but I cannot tell. For good reasons,
Marketing is in charge of releasing information. Please be patient, "you
will be richly rewarded"!

It is still an FPGA, to be configured by the customer. We are not
entering the ASIC business... ( We just want to capture more of its $$$s
)

Peter Alfke

Rahul Khanna wrote:

Xilinx seems to have launched a new architecture - ASMBL. There is no
information except a news article. Can we have more info??? Is anyone
from Xilinx Listening????

Looks like mixed jelly+peanut butter sandwich to me. Yum yum. Use as
much of each as desired.

johnjaksonATusaDOTcom

 

[John Adair]

You should have a look at EasyPath for a HardCopy equivalent. It's a bit
restricted in it's application but it exists.

John Adair
Enterpoint Ltd.
Xilinx Xpert Partners

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.


"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:MF3Eb.13446$ws.1315229@news02.tsnz.net...

Rahul Khanna wrote:
Xilinx seems to have launched a new architecture - ASMBL. There is no
information except a news article. Can we have more info??? Is anyone
from Xilinx Listening????

There was an earlier thread on this.
I did find the PDF on the Xilinx web site that was a little clearer,
as it had (virtual?) die photos.
( Web info has gone Engineering -> Marketing -> web Publishing, whilst
the PDF has only had Engineering -> Marketing 'content removal'
Info so far shows some good mechanical ideas for lowering the cost
of creating new die mixtures.
The Real Test will be the Volumes/NRE cost numbers, but they are
flag waving mainly at the ASIC customers, and remember Xilinx do not
have a HardCopy flow like Altera.
One aspect of the Xilinx approach, is it allows Hard IP, AND
keeps _some_ FPGA fabric - again, nice if you are big enough to
'get the stripes you want spun'
-jg