What is the meaning of writing a test bench in a reactive re

[parag_paul@hotmail.com]

hi All ,
I have come across the term " test bench in a reactive region "
Can nay body help me out
?
-Parag

 

[Jonathan Bromley]

On Fri, 24 Aug 2007 05:31:22 -0700, "parag_paul@hotmail.com"
<parag_paul@hotmail.com> wrote:

hi All ,
I have come across the term " test bench in a reactive region "

Yup. We have a BIG section of our SystemVerilog course on exactly
this issue. It would be dishonest to suggest that I can answer
the question in a few sentences. Maybe someone else can do better.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[jtw]

After some quick googling:
http://www.project-veripage.com/program_blocks_3.php.

The context of the link is system verilog.

JTW

<parag_paul@hotmail.com> wrote in message
news:1187958682.563823.254490@q5g2000prf.googlegroups.com...

hi All ,
I have come across the term " test bench in a reactive region "
Can nay body help me out
?
-Parag