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parag_paul@hotmail.com
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I got a verilog with the following lines
module vl_leaf( .op1(), clk);
input clk;
initial #50 $finish;
initial $display("%m from named open port module ");
always @(clk) $display ( "%m, clk = %b open port = %b time = %t ",
clk, .op1() , $time );
endmodule
What does .op1() mean
-Parag
module vl_leaf( .op1(), clk);
input clk;
initial #50 $finish;
initial $display("%m from named open port module ");
always @(clk) $display ( "%m, clk = %b open port = %b time = %t ",
clk, .op1() , $time );
endmodule
What does .op1() mean
-Parag