Guest
Hi
We are in the process of simulating a gate level post-route verilog
netlist using ncverilog. We are using SDF backannotatioon using an SDF
file generated from primetime. This is a signoff primetime run with all
parasitics and xtalk impact in it. We see a few INTERCONNECT
information in the sdf file that shows negative delay. What is the
meaning of negative delay on the interconnect. I have seen discussions
on negative delay through cells and how that has to do with the 50%
delay measurement point and the transition points on the input/output
of the cell. But what causes negative delay on the INTERCONNECT?
One example line is
(INTERCONNECT ioring\.URTRXD_pad/C BW1_BUF1008/A (-0.009::-0.009)
(0.017::0.017))
The simulator is giving a warning and making the value 0. We may not
get any problem in simulation because of that, but we are curious about
the reason.
-Dipu
We are in the process of simulating a gate level post-route verilog
netlist using ncverilog. We are using SDF backannotatioon using an SDF
file generated from primetime. This is a signoff primetime run with all
parasitics and xtalk impact in it. We see a few INTERCONNECT
information in the sdf file that shows negative delay. What is the
meaning of negative delay on the interconnect. I have seen discussions
on negative delay through cells and how that has to do with the 50%
delay measurement point and the transition points on the input/output
of the cell. But what causes negative delay on the INTERCONNECT?
One example line is
(INTERCONNECT ioring\.URTRXD_pad/C BW1_BUF1008/A (-0.009::-0.009)
(0.017::0.017))
The simulator is giving a warning and making the value 0. We may not
get any problem in simulation because of that, but we are curious about
the reason.
-Dipu