What is the meaning of negative interconnect delay in sdf fi

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Hi

We are in the process of simulating a gate level post-route verilog
netlist using ncverilog. We are using SDF backannotatioon using an SDF
file generated from primetime. This is a signoff primetime run with all
parasitics and xtalk impact in it. We see a few INTERCONNECT
information in the sdf file that shows negative delay. What is the
meaning of negative delay on the interconnect. I have seen discussions
on negative delay through cells and how that has to do with the 50%
delay measurement point and the transition points on the input/output
of the cell. But what causes negative delay on the INTERCONNECT?

One example line is

(INTERCONNECT ioring\.URTRXD_pad/C BW1_BUF1008/A (-0.009::-0.009)
(0.017::0.017))

The simulator is giving a warning and making the value 0. We may not
get any problem in simulation because of that, but we are curious about
the reason.

-Dipu
 
As a matter of fact, we're currently running into the same problem.
Although the SDF 3.0 standard may not allow negative values, the tools
simple adhere by resetting to 0. In our case we actually get violations
during simulation, while the layout tool says all should be ok.

I was thinking about propagating negative values back to the fanin or
smth, but I expect a tool to do this for me.

How do other people go about and guarantee consistency between
post-layout data and simulation data?
 
Paljas wrote:
As a matter of fact, we're currently running into the same problem.
Although the SDF 3.0 standard may not allow negative values, the tools
simple adhere by resetting to 0. In our case we actually get violations
during simulation, while the layout tool says all should be ok.

I was thinking about propagating negative values back to the fanin or
smth, but I expect a tool to do this for me.

How do other people go about and guarantee consistency between
post-layout data and simulation data?
As I know, vcs has a switch -negdelay which will take care of the
negative delays in sdf file.
 

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