What is the meaning of 'combinatorial path crossing multiple

[shjin]

Hi, all.

I got some error message when I use HDL Analysis and Lint (HAL) tool
from Cadence on my design.

It is,
"Combinatorial path crossing multiple units drives a signal. The
driver of flip-flop/output port has combinatorial assignment at
multiple hierarchy levels."

Since the code is just a normal register - combinational logic -
register style, it seems usual to me.

Can anybody explain why the analysis tool makes an error on this?

Thanks in advance.

- shjin

 

[HT-Lab]

"shjin" <seunghun.jin@gmail.com> wrote in message
news:07aef7e1-bb1b-4f98-95cd-af24ab4a96ad@k22g2000yqh.googlegroups.com...

Hi, all.

I got some error message when I use HDL Analysis and Lint (HAL) tool
from Cadence on my design.

It is,
"Combinatorial path crossing multiple units drives a signal. The
driver of flip-flop/output port has combinatorial assignment at
multiple hierarchy levels."

Since the code is just a normal register - combinational logic -
register style, it seems usual to me.

Can anybody explain why the analysis tool makes an error on this?

You seem to have a long combinatorial path going through multiple modules
without a FF. This error message might be triggered by a HAL rule which states
that each output (or input) port needs to be registered. I would change this
rule to a warning and when you come to synthesis and look at your critical path
you might remember this warning

Hans
www.ht-lab.com

Thanks in advance.

- shjin

 

[jc]

On Nov 17, 6:58 pm, shjin <seunghun....@gmail.com> wrote:

Hi, all.

I got some error message when I use HDL Analysis and Lint (HAL) tool
from Cadence on my design.

It is,
"Combinatorial path crossing multiple units drives a signal. The
driver of flip-flop/output port has combinatorial assignment at
multiple hierarchy levels."

Since the code is just a normal register - combinational logic -
register style, it seems usual to me.

Can anybody explain why the analysis tool makes an error on this?

Thanks in advance.

- shjin

The warning seems to hint that you are driving an output port with a
combinatorial path that consists of multiple logic levels, which
correlates to longer flop-to-flop delays and slower performance. Good
practice to register that output port to (1) beef up performance, and
(2) to allow destination module that is receiving that signal to deal
with clk-to-out delay out of your module. Gives floorplanning more
flexibility as well. Do it now, or spend many hours during timing
closure later...
John