P
parag_paul@hotmail.com
Guest
Hi All,
Is a signal in VHDL supposed to mean that we have a source in the
entity somewhere. Can there be any Verilog analogy to the signal in
VHDL
-Parag
Is a signal in VHDL supposed to mean that we have a source in the
entity somewhere. Can there be any Verilog analogy to the signal in
VHDL
-Parag