what is the longest static prefix of an expression

P

parag

Guest
I have been seeing this term rather frequently but never got a chance
to understand what it means.
can some one please help me understand , longest static prefix of an
expression means
 
On Wed, 9 Sep 2009 23:45:01 -0700 (PDT), parag <parag.paul@gmail.com>
wrote:

I have been seeing this term rather frequently but never got a chance
to understand what it means.
can some one please help me understand , longest static prefix of an
expression means
In Verilog it's common to find something in the hierarchy,
using static references:
top_mod.child_inst.inner_inst.some_var
and then index off it using something dynamic that can
change at runtime:
top_mod.child_inst.inner_inst.some_var[other_var]

If Verilog needs to build a static structure, such as
the sensitivity list of an always_comb, it clearly
cannot use the dynamic information [other_var] when
doing that - the information is simply not available
at elaboration time, when the static structures are
built. In an attempt to handle this in a uniform
way across what is now a very complex language, the
idea of "longest static prefix" was introduced (or,
if you like, stolen from VHDL). The idea is that
you start at the beginning of the reference, and
stop as soon as you find something dynamic, so
Verilog knows as much detail as it possibly can
before the simulation starts to run. It is this
longest static prefix that is used to determine...
- what appears in an always_comb sensitivity list
- whether there are multiple procedural drivers
on a variable (which, of course, is prohibited
in some situations)
and a few other things that I would need to check
in the LRM.

Here's a SystemVerilog example to try to illustrate
some of the ideas;

typedef struct {
int x;
byte b[0:7];
} xb;

xb xb_array[10]; // array [0:9] of xb

int index1, index2;

assign xb_array[5].x = xb_array[6].x;
// OK, everything is static

always_comb
xb_array[4].x = xb_array[index1].x;
// The whole of xb_array must be in the
// sensitivity list, because index1 is not static

assign xb_array[3].b[0] = 0;
// everything is static

always_comb begin
xb_array[index2].b[5] = 0;
// illegal; this represents a procedural driver
// on the whole of xb_array because [index2] is not
// static, so the longest static prefix is just xb_array

Full details in the LRM, as of course you're aware.
The existence of classes and virtual interfaces makes this
even more "interesting" :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Sep 10, 12:25 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Wed, 9 Sep 2009 23:45:01 -0700 (PDT), parag <parag.p...@gmail.com
wrote:

I have been seeing this term rather frequently but never got a chance
to understand what it means.
can some one please help me understand , longest static prefix of an
expression means

In Verilog it's common to find something in the hierarchy,
using static references:
  top_mod.child_inst.inner_inst.some_var
and then index off it using something dynamic that can
change at runtime:
  top_mod.child_inst.inner_inst.some_var[other_var]

If Verilog needs to build a static structure, such as
the sensitivity list of an always_comb, it clearly
cannot use the dynamic information [other_var] when
doing that - the information is simply not available
at elaboration time, when the static structures are
built.  In an attempt to handle this in a uniform
way across what is now a very complex language, the
idea of "longest static prefix" was introduced (or,
if you like, stolen from VHDL).  The idea is that
you start at the beginning of the reference, and
stop as soon as you find something dynamic, so
Verilog knows as much detail as it possibly can
before the simulation starts to run.  It is this
longest static prefix that is used to determine...
- what appears in an always_comb sensitivity list
- whether there are multiple procedural drivers
  on a variable (which, of course, is prohibited
  in some situations)
and a few other things that I would need to check
in the LRM.

Here's a SystemVerilog example to try to illustrate
some of the ideas;

  typedef struct {
    int x;
    byte b[0:7];
  } xb;

  xb xb_array[10];  // array [0:9] of xb

  int index1, index2;

  assign xb_array[5].x = xb_array[6].x;
  // OK, everything is static

  always_comb
    xb_array[4].x = xb_array[index1].x;
  // The whole of xb_array must be in the
  // sensitivity list, because index1 is not static

  assign xb_array[3].b[0] = 0;
  // everything is static

  always_comb begin
    xb_array[index2].b[5] = 0;
    // illegal; this represents a procedural driver
    // on the whole of xb_array because [index2] is not
    // static, so the longest static prefix is just xb_array

Full details in the LRM, as of course you're aware.
The existence of classes and virtual interfaces makes this
even more "interesting" :)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Thanks a lot Jonathan,
That helps a lot, surprisingly I found it somewhere in the context of
always_comb itself and you used the same context
 

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