S
samuel
Guest
Hi,
As I know, we can write the verification ip such ahb slave/master/
monitor in verilog/vhdl or whatever language. And in systermverilog ,
I guess we still can implement this kind of traditional vip , besides
assertion based vip.
My question is : What is the differences between a assertion vip and a
tranditional vip? How to identify a vip written by systemverilog is a
tranditional vip or a assertion based one ?
As I know, we can write the verification ip such ahb slave/master/
monitor in verilog/vhdl or whatever language. And in systermverilog ,
I guess we still can implement this kind of traditional vip , besides
assertion based vip.
My question is : What is the differences between a assertion vip and a
tranditional vip? How to identify a vip written by systemverilog is a
tranditional vip or a assertion based one ?