What is the content of "High-speed SERDES interfacing such a

[fl]

Hi,
I read a job post which requires:

High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI


I know FPGA vendors have PCIe IP interfaces. What is the job content with the
above statements? It requires the engineer to design a PCIe, SDI, SGMII and XAUI
interfaces in house? Or it can accept to use third party IP?

Thanks for explain it to me.

 

[Ed McGettigan]

On Friday, August 8, 2014 4:33:32 AM UTC-7, fl wrote:

Hi,

I read a job post which requires:



High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI





I know FPGA vendors have PCIe IP interfaces. What is the job content with the

above statements? It requires the engineer to design a PCIe, SDI, SGMII and XAUI

interfaces in house? Or it can accept to use third party IP?



Thanks for explain it to me.

This is probably a case of "if you have to ask you don't have the experience".

Using the question as a search term in Google turns up a job posting for Creston looking for people with Xilinx or Altera experience as the first bullet item, so this likely means that you have actual experience use the MGT, Multi-Gigabit Transceivers, in a real world project implementing one or more of the listed protocols.

Ed McGettigan
--
Xilinx Inc.