J
Jeff Mucha
Guest
I am designing a power supply using a standard buck topology with
synchronous FETs.
I'm trying to minimize power in the drivers of the gate of the FETs, some of
the datasheets say minimize the gate charge of the control fet. Some say to
minimize the reverse transfer capacitance.
Can you just assume Q=CV and then figure out what the driver impedance is
and estimate power lost through the equivalent output resistor in the gate
driver? I'm sure it is more complicated than that, but can anyone provide
some insight for me?
Thanks,
Jeff
synchronous FETs.
I'm trying to minimize power in the drivers of the gate of the FETs, some of
the datasheets say minimize the gate charge of the control fet. Some say to
minimize the reverse transfer capacitance.
Can you just assume Q=CV and then figure out what the driver impedance is
and estimate power lost through the equivalent output resistor in the gate
driver? I'm sure it is more complicated than that, but can anyone provide
some insight for me?
Thanks,
Jeff