what is problem in this code....

[sheri]

hi all,
there is some problem in the following code which i could not figure
it out..I have synthesised this code in xilinx XST..The scehamtics
shown is wrong..So please help me to solve this..thanks in advance..

entity simple_design is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : out STD_LOGIC;

e : out STD_LOGIC);

end simple_design;



architecture Behavioral of simple_design is



procedure logic (

signal a : in std_logic;

signal b : in std_logic;

signal c : in std_logic;

signal x : out std_logic

) is

begin

x <= a and b and c;

end procedure logic;



begin



logic_P:

process (a, b, c)

begin

d <= a xor b xor c;

logic (

a => a,

b => b,

c => c,

x => e

);

end process logic_P;



end architecture Behavioral;

 

[Brian Drummond]

On Thu, 1 Jan 2009 03:22:07 -0800 (PST), sheri
<saras_rajgiri@yahoo.co.in> wrote:

hi all,
there is some problem in the following code which i could not figure
it out..I have synthesised this code in xilinx XST..The scehamtics
shown is wrong..So please help me to solve this..thanks in advance..

Questions:
(0) stupid Q first: it isn't simply "and" in the proc vs "xor" in the
process?
(1) does it work in simulation?
(2) does a post-synthesis netlist from XST simulate correctly?
and (3) what is it doing differently to your expectation?

Answer these questions and file a Webcase with Xilinx.
Also add the same logic from the procedure in the body of the process,
driving a different output. Then compare the two outputs in a testbench.
Test with both input and post-synth netlist; the former may pass, the
latter may fail.

XST is known to have problems when you pass signals as arguments into a
procedure; specifically it uses variable assignment rules (immediate
assignment) instead of signal assignment (postponed assignment
scheduling). This bug has been observed in ISE 7.1 through 10.1sp3 (8.x
untested), reported as Webcase 753604 and a Change Request (CR #493483)
filed.

Interestingly Xilinx tried to argue this wasn't a bug...

The XST experts are currently investigation and some actually disagree
with you and with Synplify and Precision's results.
.... until it was pointed out that the results also contradicted both

Modelsim and Xilinx's own ISIM simulator.

Now this specific bug would result in x (=> e) being immediately
updated. In a clocked process that would make it appear one cycle early.
However I can't see what difference that would make in this
combinatorial process.

So I am interested to know what you are seeing.

- Brian.

 

[Brad Smallridge]

I have synthesised this code in xilinx XST..The scehamtics
shown is wrong.

The RTL schematic shows three inputs A, B, and C with two
outputs D and E. What did you expect? );

Brad Smallridge
Ai Vision