What is "peak diode recovery dV/dt" ???

[Chris Carlen]

Greetings:

I was trying to figure out why I had a 1us shoot-through in a simulation
of an H-bridge using IRFP260N FETs.

Since I never really understood diode reverse recovery time, yesterday I
figured I better make sense of it because it was probably related to my
H-bridge misbehavior. So I measured t_rr of some diodes. Now I
understand very well. The darn things don't turn off when you tell them
to. Then I simulated the bench circuit using LTSpice. I found things
agreed fairly well for some diodes.

Then in LTSpice I stuck in an IRFP260N FET with the gate tied to the
source with a 1 ohm resistor. I would estimate that means it's pretty
well turned off. Unfortunately, it never turns off. In fact, my model
must be horribly broken. My IRF540 model works fine. They are the only
two I tried from the model files I downloaded from IRF. I have had
considerable troubles with them before, as I recall. I now think my
H-bridge problem is actually a broken FET model rather than anything
else. I will confirm this when I get another chance to tinker with it.

But about the dV/dt: I think it means the peak slope of the voltage
rise across the diode as it is turning off. But this is a guess.

So what is "peak diode recovery dV/dt," and what is its significance?

Thanks.


--
_____________________
Christopher R. Carlen
crobc@earthlink.net
Suse 8.1 Linux 2.4.19

 

[John Larkin]

On Fri, 26 Mar 2004 20:13:57 -0800, Chris Carlen
<crobc@BOGUS_FIELD.earthlink.net> wrote:

Greetings:

I was trying to figure out why I had a 1us shoot-through in a simulation
of an H-bridge using IRFP260N FETs.

Since I never really understood diode reverse recovery time, yesterday I
figured I better make sense of it because it was probably related to my
H-bridge misbehavior. So I measured t_rr of some diodes. Now I
understand very well. The darn things don't turn off when you tell them
to. Then I simulated the bench circuit using LTSpice. I found things
agreed fairly well for some diodes.

Then in LTSpice I stuck in an IRFP260N FET with the gate tied to the
source with a 1 ohm resistor. I would estimate that means it's pretty
well turned off. Unfortunately, it never turns off. In fact, my model
must be horribly broken. My IRF540 model works fine. They are the only
two I tried from the model files I downloaded from IRF. I have had
considerable troubles with them before, as I recall. I now think my
H-bridge problem is actually a broken FET model rather than anything
else. I will confirm this when I get another chance to tinker with it.

But about the dV/dt: I think it means the peak slope of the voltage
rise across the diode as it is turning off. But this is a guess.

So what is "peak diode recovery dV/dt," and what is its significance?

Thanks.

I did a fet h-bridge motor driver a while back, and blew a lot of fets
at very low operating currents. Seems that the motor back EMF would
forward-bias the fet substrate diodes, and then they would snap off
some time after the current returned to "normal" polarity. The
resulting dv/dt was huge, and blew out the gates. This was some years
ago, and I think most fets are better now: softer substrate diode
recovery and tougher gates. But I think that very high dv/dt,
happening when the substrate diodes snap out of reverse conduction,
can be dangerous.

John

 

[John Popelish]

Chris Carlen wrote:

Greetings:

I was trying to figure out why I had a 1us shoot-through in a simulation
of an H-bridge using IRFP260N FETs.

Since I never really understood diode reverse recovery time, yesterday I
figured I better make sense of it because it was probably related to my
H-bridge misbehavior. So I measured t_rr of some diodes. Now I
understand very well. The darn things don't turn off when you tell them
to. Then I simulated the bench circuit using LTSpice. I found things
agreed fairly well for some diodes.

Then in LTSpice I stuck in an IRFP260N FET with the gate tied to the
source with a 1 ohm resistor. I would estimate that means it's pretty
well turned off. Unfortunately, it never turns off. In fact, my model
must be horribly broken. My IRF540 model works fine. They are the only
two I tried from the model files I downloaded from IRF. I have had
considerable troubles with them before, as I recall. I now think my
H-bridge problem is actually a broken FET model rather than anything
else. I will confirm this when I get another chance to tinker with it.

But about the dV/dt: I think it means the peak slope of the voltage
rise across the diode as it is turning off. But this is a guess.

So what is "peak diode recovery dV/dt," and what is its significance?

Thanks.

Yes, dv/dt means the time rate of change of voltage.

When they are forward biased, the N layer injects electrons into the
junction and the P region injects holes. As these mingle, they join
and eliminate each other, making room for more to enter the junction,
and this process represents the passage of current through the
junction.

When you apply reverse bias to the junction, the electrons head back
toward the N region, and the holes head back toward the P region, and
as long as they are arriving, there is current passing through the
connections. But when the stored supply of these carriers finally
runs out, the diode suddenly becomes non conducting and the reverse
voltage can rise very fast. If your circuit design limits both the
peak reverse current just after voltage reversal, and the rate of rise
of voltage as the carriers are disappearing, then the reverse current
is not so violent and the voltage rise not so damaging when conduction
ceases. Fast recovery diodes do not necessarily eliminate this
problem, but reduce the time the circuit haves to take to avoid the
problems.

It may help to think of the diode as a check valve that has flow
backward momentarily before the ball reaches the seat and the voltage
spike as the water hammer that occurs at that moment of contact.

As to your fet not shutting off, are you sure of its polarity?

--
John Popelish

 

[Chris Carlen]

John Popelish wrote:

Yes, dv/dt means the time rate of change of voltage.

When they are forward biased, the N layer injects electrons into the
junction and the P region injects holes. As these mingle, they join
and eliminate each other, making room for more to enter the junction,
and this process represents the passage of current through the
junction.

When you apply reverse bias to the junction, the electrons head back
toward the N region, and the holes head back toward the P region, and
as long as they are arriving, there is current passing through the
connections. But when the stored supply of these carriers finally
runs out, the diode suddenly becomes non conducting and the reverse
voltage can rise very fast. If your circuit design limits both the
peak reverse current just after voltage reversal, and the rate of rise
of voltage as the carriers are disappearing, then the reverse current
is not so violent and the voltage rise not so damaging when conduction
ceases. Fast recovery diodes do not necessarily eliminate this
problem, but reduce the time the circuit haves to take to avoid the
problems.

The mechanism of operation you have elucidated in a very straightforward
manner.

Ok, so the point is that the peak dV/dt is something that must be heeded
in order to avoid breaking the device, right?

It may help to think of the diode as a check valve that has flow
backward momentarily before the ball reaches the seat and the voltage
spike as the water hammer that occurs at that moment of contact.

As to your fet not shutting off, are you sure of its polarity?

Well, this was simulation, so pretty hard to screw up the wiring. Also,
it works fine with another model. Let me go to irf.com and see if I
can't replace this model...

No luck. The file available for IRFP260N is the same one I have
already, as I figured. I will post the files for the broken simulation
on sci.electronics.cad

Thanks for the input on the diode parameter


Good day!


--
_____________________
Christopher R. Carlen
crobc@earthlink.net
Suse 8.1 Linux 2.4.19

 

[John Popelish]

Chris Carlen wrote:

John Popelish wrote:

The mechanism of operation you have elucidated in a very straightforward
manner.

Ok, so the point is that the peak dV/dt is something that must be heeded
in order to avoid breaking the device, right?

Higher dv/dt will not necessarily hurt the diode but may well hurt the
fet in parallel with it, or increase the diode heating. You design a
snubber to keep the dv/dt below the specified maximum.

(snip)

--
John Popelish