What is MPGA?

[Kuan Zhou]

Hi,
I am wondering what's the difference between MPGA and FPGA?
MPGA is Mask Programmed Gate Array. What does Mask mean here?



sincerely
-------------
Kuan Zhou
ECSE department

 

[Peter Alfke]

A mask-programmable gate array uses one (or more) metal mask in the IC
manufacturing process, to achieve the intended functionality.

In an FPGA, the user programs a standard off-the shelf chip, either by
loading a bitstream into latches, or into Flash cells, or by programming
antifuses.
The manufacturer just provides software support.
Peter Alfke

From: Kuan Zhou <zhouk@rpi.edu
Organization: Rensselaer Polytechnic Institute, Troy NY, USA
Newsgroups: comp.arch.fpga
Date: Thu, 22 Apr 2004 17:39:53 -0400
Subject: What is MPGA?

Hi,
I am wondering what's the difference between MPGA and FPGA?
MPGA is Mask Programmed Gate Array. What does Mask mean here?



sincerely
-------------
Kuan Zhou
ECSE department

 

[glen herrmannsfeldt]

Someone wrote:

I am wondering what's the difference between MPGA and FPGA?
MPGA is Mask Programmed Gate Array. What does Mask mean here?

Peter Alfke wrote:

A mask-programmable gate array uses one (or more) metal mask in the IC
manufacturing process, to achieve the intended functionality.

In an FPGA, the user programs a standard off-the shelf chip, either by
loading a bitstream into latches, or into Flash cells, or by programming
antifuses.
The manufacturer just provides software support.

If I remember this right, originally there were Gate Arrays,
which were actually closer to transistor arrays. Everything needed
to make logic circuits except the metal layer. (Maybe only one
or two at the time.) NRE costs are lower than standard cell
or custom logic, though usable density was a little lower, too.

Then along came FPGA's, so the original ones have been renamed?

-- glen

 

[Jeff Cunningham]

If I remember this right, originally there were Gate Arrays,
which were actually closer to transistor arrays. Everything needed
to make logic circuits except the metal layer. (Maybe only one
or two at the time.) NRE costs are lower than standard cell
or custom logic, though usable density was a little lower, too.

Then along came FPGA's, so the original ones have been renamed?
-- glen

I have run across the term "structured asic" these days but never really
found a definition of it. Is structured asic simply what we used to call
a gate array (fixed cell size cusomization of metal only)?

-Jeff

 

[Kuan Zhou]

Hi,
Does it mean in MPGA the program process can be done only once,
and it can only done on the foundry side?

sincerely
-------------
Kuan Zhou
ECSE department


On Thu, 22 Apr 2004, Peter Alfke wrote:

A mask-programmable gate array uses one (or more) metal mask in the IC
manufacturing process, to achieve the intended functionality.

In an FPGA, the user programs a standard off-the shelf chip, either by
loading a bitstream into latches, or into Flash cells, or by programming
antifuses.
The manufacturer just provides software support.
Peter Alfke

From: Kuan Zhou <zhouk@rpi.edu
Organization: Rensselaer Polytechnic Institute, Troy NY, USA
Newsgroups: comp.arch.fpga
Date: Thu, 22 Apr 2004 17:39:53 -0400
Subject: What is MPGA?

Hi,
I am wondering what's the difference between MPGA and FPGA?
MPGA is Mask Programmed Gate Array. What does Mask mean here?



sincerely
-------------
Kuan Zhou
ECSE department

 

[Peter Alfke]

Hi,
Does it mean in MPGA the program process can be done only once,
and it can only done on the foundry side?

Yes, and that's why FPGAs have become so popular. The user can make the
change, and (except for antifuse FPGAs) the chip can be reprogrammed an
unlimited number of times.
Peter Alfke

 

[Ken McElvain]

Jeff Cunningham wrote:

If I remember this right, originally there were Gate Arrays,
which were actually closer to transistor arrays. Everything needed
to make logic circuits except the metal layer. (Maybe only one
or two at the time.) NRE costs are lower than standard cell
or custom logic, though usable density was a little lower, too.

Then along came FPGA's, so the original ones have been renamed?
-- glen



I have run across the term "structured asic" these days but never really
found a definition of it. Is structured asic simply what we used to call
a gate array (fixed cell size cusomization of metal only)?

A structured ASIC requires only a subset of masks to customize. You might
have two metal layers and 1 or two via layers for customization. This
lowers NRE charges and improves turn around time. Equally important,
structured ASICs take care of power distribution, clock distribution, test,
and signal integrity issues via a combination of architecture and tools.
There is also a lot of focus on accuracy of pre-handoff timing prediction
based on placement so that the handoff is in one direction only.
From a design tasks point of view it it similar to an FPGA. You obviously
lose reprogramability, so if you like debugging live hardware, you
will want to use one or more FPGAs to prototype.

-Jeff