what is meant by the following piece of System Verilog code

[very_log]

struct {
int a, b, c;
} str1 = '{1, 2, 3};
int x1, x2, x3;

x1 = str1 matches '{a:1, b:.n} &&& str1 matches '{b:2, c:.m} ? m*n : 0;

 

[Jonathan Bromley]

On Fri, 30 Nov 2007 07:25:53 -0800 (PST), very_log
<sachin.goyal.new@gmail.com> wrote:

struct {
int a, b, c;
} str1 = '{1, 2, 3};
int x1, x2, x3;

x1 = str1 matches '{a:1, b:.n} &&& str1 matches '{b:2, c:.m} ? m*n : 0;

Which bit of it don't you follow? There are at least
five new SystemVerilog constructs at work here:

- struct
- assignment pattern '{...}
- pattern matching using the "matches" operator
- logical "and" on pattern matches using &&&
- pattern capture using the ".n" syntax

All of them are fully documented in the LRM.

The last time I checked, tool support for "matches" was
very limited.
--
Jonathan Bromley, Consultant

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