what is executed first?

[Michael]

Are these line equivalent?

1. reg a = 0;
2. reg a; initial a = 0;

What happen in this case?
reg b = 0; initial b = 1;

Thanks.

 

[Stephen Williams]

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Michael wrote:

Are these line equivalent?

1. reg a = 0;
2. reg a; initial a = 0;

Yes.

What happen in this case?
reg b = 0; initial b = 1;

It's a race.

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Michael wrote:

Are these line equivalent?

1. reg a = 0;
2. reg a; initial a = 0;

They are equivalent in Verilog. They are not quite equivalent in
SystemVerilog.

What happen in this case?
reg b = 0; initial b = 1;

In Verilog, this is a race condition and either could execute first.
In SystemVerilog the initializer is required to execute first.

 

[Michael]

What about

reg b = 0; initial b <= 1;


sharp@cadence.com wrote:

Michael wrote:
Are these line equivalent?

1. reg a = 0;
2. reg a; initial a = 0;

They are equivalent in Verilog. They are not quite equivalent in
SystemVerilog.

What happen in this case?
reg b = 0; initial b = 1;

In Verilog, this is a race condition and either could execute first.
In SystemVerilog the initializer is required to execute first.

 

Michael wrote:

What about

reg b = 0; initial b <= 1;

This will guarantee a final result of 1, due to the delaying of
nonblocking assignments to the nonblocking event queue.

 

[Michael]

Thank you.

What about:
reg b;
initial b = 0;
initial b <= 1;

I believe b should be 1.

This should be the same result. Isn't it?
reg b;
initial b <= 1;
initial b = 0;



sharp@cadence.com wrote:

Michael wrote:
What about

reg b = 0; initial b <= 1;

This will guarantee a final result of 1, due to the delaying of
nonblocking assignments to the nonblocking event queue.

 

[Chris F Clark]

"Michael" <michaelst@gmail.com> writes:

Thank you.

What about:
reg b;
initial b = 0;
initial b <= 1;

I believe b should be 1.

This should be the same result. Isn't it?
reg b;
initial b <= 1;
initial b = 0;

Yes, the textual order of the statements (within a module) makes no
difference. (Textual order within an initial or always block does
make a difference, but initial and always blocks (and several other
module level constructs, such as assign statements and instantiations)
can be sorted in any order without affecting the language defined
behaviour.)

However, the question is why you would care, unless you are
implementing a verilog tool (e.g. a simulator, a synthesizer, an
equivalence checker, ...) or you are looking at poorly written
verilog?

In particular, you can't write both statements in synthesizable code,
because most synthesizers don't like:
1) signals driven by two different blocks
2) signals driven by both blocking and non-blocking assigns
3) initial statements in general

Next, assuming you are writing test bench code, what behavior of the
device under test are you trying to elicit with the various
assignments? It is very unlikely that whatever behaviour you are
trying to test will actually be exhibited by a hardware (synthesized)
version, since you don't have control over the generated logic which
is fine-grained enough to catch the momentary glitches such signals
exhibit. And, if you are testing your logic against such glitches, it
is unlikely that the language gives you enough power to model the
details one would need to describe to catch the nuances such hardware
is likely to exhibit, since analog characteristics are likely to come
into play.

In other words, the semantics of verilog don't correspond to hardware
AT THAT LEVEL OF DETAIL. You can describe things in verilog you can't
build and you can build things you can't describe in verilog.

Thus, you really shouldn't care about those details. You shouldn't be
writing Verilog code where those details matter. Not if you are trying to
create circuits which actually work reliably.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

[Michael]

Dear Chris,

Certainly this code is not synthesizable. I'm going to use this
construction for testbench.

 

Michael wrote:

Thank you.

What about:
reg b;
initial b = 0;
initial b <= 1;

I believe b should be 1.

This should be the same result. Isn't it?
reg b;
initial b <= 1;
initial b = 0;

Yes, the delay to the nonblocking event queue will cause the
nonblocking assignment to finish last in both cases.

Note that the order of execution of two initial blocks is undefined in
the language, so they could execute in either order regardless of the
order they appear in the source. A particular implementation might
always execute them in a particular order, such as source order, but
the language does not guarantee it.