W
Weng Tianxiang
Guest
Hi,
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
Navigation
Install the app
How to install the app on iOS
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
More options
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an alternative browser.
You should upgrade or use an alternative browser.
What is called carry chain structure in FPGA is called in IC
J
John_H
Guest
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
Depending on the library, you may have carry look-ahead structures
implemented or other optimized structures. It ends up as logic but with
ASIC specific implementation brought on by the library optimizations.
news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
Logic?Hi,
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
Depending on the library, you may have carry look-ahead structures
implemented or other optimized structures. It ends up as logic but with
ASIC specific implementation brought on by the library optimizations.
W
Weng Tianxiang
Guest
On Sep 10, 1:57 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
Is it called priority tree?
Weng
Hi John_H,"Weng Tianxiang" <wtx...@gmail.com> wrote in message
news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
Hi,
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
Logic?
Depending on the library, you may have carry look-ahead structures
implemented or other optimized structures. It ends up as logic but with
ASIC specific implementation brought on by the library optimizations.
Is it called priority tree?
Weng
J
John_H
Guest
Weng Tianxiang wrote:
if/else blocks or case statements) would be used to implement the carry
structure in ASIC-optimized netlists.
There is no single answer for your query. It will be vendor-specific
since different compilers will optimize the code to different optimized
libraries.
It's possible - though unlikely - that a priority tree (often used forOn Sep 10, 1:57 pm, "John_H" <newsgr...@johnhandwork.com> wrote:
"Weng Tianxiang" <wtx...@gmail.com> wrote in message
news:1189440832.554409.102540@g4g2000hsf.googlegroups.com...
Hi,
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
Logic?
Depending on the library, you may have carry look-ahead structures
implemented or other optimized structures. It ends up as logic but with
ASIC specific implementation brought on by the library optimizations.
Hi John_H,
Is it called priority tree?
Weng
if/else blocks or case statements) would be used to implement the carry
structure in ASIC-optimized netlists.
There is no single answer for your query. It will be vendor-specific
since different compilers will optimize the code to different optimized
libraries.
P
Peter Alfke
Guest
On Sep 10, 9:13 am, Weng Tianxiang <wtx...@gmail.com> wrote:
facilitates binary addition and subtraction, where any bit position
can affect the next higher bit position with a binary carry or borrow
signal.
The physical implementation can vary a lot, using different
compromises between speed and complexity (and perhaps power
consumption). There is ripple carry, carry look-ahead, carry
anticipate, and even more exotic methods. The FPGAs I am familiar with
use carry-look-ahead over 2 or 4 bits, which is just one step ahead of
the simplest ripple-carry. But since the FPGA carry structure is hard-
wired, it usually is faster than any more exotic scheme, if ithat were
implemented in an FPGA. At least in the usual range below 32 bits...
ASIC trade-offs are different.
Peter Alfke
Weng, the objective of the carry chain is easily defined: ItHi,
I want to know what is called carry chain structure in FPGA is called
in IC?
Thank you.
Weng
facilitates binary addition and subtraction, where any bit position
can affect the next higher bit position with a binary carry or borrow
signal.
The physical implementation can vary a lot, using different
compromises between speed and complexity (and perhaps power
consumption). There is ripple carry, carry look-ahead, carry
anticipate, and even more exotic methods. The FPGAs I am familiar with
use carry-look-ahead over 2 or 4 bits, which is just one step ahead of
the simplest ripple-carry. But since the FPGA carry structure is hard-
wired, it usually is faster than any more exotic scheme, if ithat were
implemented in an FPGA. At least in the usual range below 32 bits...
ASIC trade-offs are different.
Peter Alfke
C
comp.arch.fpga
Guest
On 10 Sep., 18:13, Weng Tianxiang <wtx...@gmail.com> wrote:
In most libraries it is part of the full adder cell.
While in general it is good for performance to have skewed cells that
provide
one path through the adder that is a lot faster than the other passes,
it turns
out that many mappers do not handle that case well. Therefore often
only
symetric cells are available. (Which are good for multipliers).
What the other posters mentioned actually are alternative carry
structures that
are not chains.
Kolja Sulimma
It is called a carry chain.Hi,
I want to know what is called carry chain structure in FPGA is called
in IC?
In most libraries it is part of the full adder cell.
While in general it is good for performance to have skewed cells that
provide
one path through the adder that is a lot faster than the other passes,
it turns
out that many mappers do not handle that case well. Therefore often
only
symetric cells are available. (Which are good for multipliers).
What the other posters mentioned actually are alternative carry
structures that
are not chains.
Kolja Sulimma
G
glen herrmannsfeldt
Guest
Peter Alfke wrote:
(snip on carry generation in FPGAs)
select using pass transistors. I haven't looked at the
newer series, I don't believe that they are documented as well
as the older ones. I used to do work on designs that used the
properties of the XC4000 carry chain. Since the carry logic
was separate from the CLB logic, one could use it, for example,
to compare two values without computing the difference.
-- glen
(snip on carry generation in FPGAs)
I thought the XC4000 series was a specialized form of carryThe physical implementation can vary a lot, using different
compromises between speed and complexity (and perhaps power
consumption). There is ripple carry, carry look-ahead, carry
anticipate, and even more exotic methods.
select using pass transistors. I haven't looked at the
newer series, I don't believe that they are documented as well
as the older ones. I used to do work on designs that used the
properties of the XC4000 carry chain. Since the carry logic
was separate from the CLB logic, one could use it, for example,
to compare two values without computing the difference.
-- glen