Y
Yakovm3@gmail.com
Guest
Hello
What is a difference between an array of instance and generate for
loop?
Thank you
What is a difference between an array of instance and generate for
loop?
Thank you
Navigation
Install the app
How to install the app on iOS
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
More options
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an alternative browser.
You should upgrade or use an alternative browser.
What is a difference between an array of instance and genera
J
Jonathan Bromley
Guest
On Sun, 18 Jul 2010 10:02:52 -0700 (PDT), "Yakovm3@gmail.com" wrote:
because instance arrays have very rigid rules about how the
ports of the instances should be connected (although those
rules do what's needed in almost all the common cases).
Generates allow you to put more than just the module instance
in each "iteration" of the loop. This can be very useful
when, for example, you need some glue logic associated with
each instance in the array.
But generate's flexibility comes at a price. The body of
a generate loop is a new, named scope. So the names of the
instances are rather complicated:
module M(...);
endmodule
module uses_many_M;
...
M [3:0] M_array (...); // creates instances
// M_array[0], M_array[1], ...
...
generate
genvar i;
for (i=0; i<=3; i++) begin: gen_inst
M M_gen(...); // instance gen_inst[0].M_gen, etc
end
endgenerate
...
endmodule
In Verilog-2005 the requirement to name the begin..end
block was dropped, but if you don't provide a name the
compiler will provide one for you, so you can't get
away from the extra level of scope.
For synthesis, where you never make dotted name
references, the extra level of scope probably doesn't
matter unless you're inspecting the post-synthesis
netlist. For simulation, though, the added complexity
can be tiresome if you want to make cross-module
reference into one of the generated module instances.
--
Jonathan Bromley
Generate loops are somewhat more flexible than instance arrays,What is a difference between an array of instance and generate for
loop?
because instance arrays have very rigid rules about how the
ports of the instances should be connected (although those
rules do what's needed in almost all the common cases).
Generates allow you to put more than just the module instance
in each "iteration" of the loop. This can be very useful
when, for example, you need some glue logic associated with
each instance in the array.
But generate's flexibility comes at a price. The body of
a generate loop is a new, named scope. So the names of the
instances are rather complicated:
module M(...);
endmodule
module uses_many_M;
...
M [3:0] M_array (...); // creates instances
// M_array[0], M_array[1], ...
...
generate
genvar i;
for (i=0; i<=3; i++) begin: gen_inst
M M_gen(...); // instance gen_inst[0].M_gen, etc
end
endgenerate
...
endmodule
In Verilog-2005 the requirement to name the begin..end
block was dropped, but if you don't provide a name the
compiler will provide one for you, so you can't get
away from the extra level of scope.
For synthesis, where you never make dotted name
references, the extra level of scope probably doesn't
matter unless you're inspecting the post-synthesis
netlist. For simulation, though, the added complexity
can be tiresome if you want to make cross-module
reference into one of the generated module instances.
--
Jonathan Bromley
F
fpgabuilder
Guest
On Jul 18, 10:02 am, "Yako...@gmail.com" <yako...@gmail.com> wrote:
E.g. a multiport arbiter that has req and gnt. In this case you can
declare the interface as an array in the arbiter module. And then in
the top-level you could connect to individual interfaces from a
generate block.
/////
module top
#(parameter NUM_OF_PORTS = 4)
(
...
);
arb_if inst_arb_if [NUM_OF_PORTS-1:0]();
genvar i;
generate for (i=0;i<NUM_OF_PORTS;i+=1) begin : proc_blk
processor inst_processor (
.arb_if (inst_arb_if)
);
end
endgenerate
arbiter
#(.NUM_OF_PORTS(NUM_OF_PORTS) )
inst_arbiter (
.arb_if (inst_arb_if)
);
endmodule
Arrays can help out when you have multiple instances of an interfaces.Hello
What is a difference between an array of instance and generate for
loop?
Thank you
E.g. a multiport arbiter that has req and gnt. In this case you can
declare the interface as an array in the arbiter module. And then in
the top-level you could connect to individual interfaces from a
generate block.
/////
module top
#(parameter NUM_OF_PORTS = 4)
(
...
);
arb_if inst_arb_if [NUM_OF_PORTS-1:0]();
genvar i;
generate for (i=0;i<NUM_OF_PORTS;i+=1) begin : proc_blk
processor inst_processor (
.arb_if (inst_arb_if)
);
end
endgenerate
arbiter
#(.NUM_OF_PORTS(NUM_OF_PORTS) )
inst_arbiter (
.arb_if (inst_arb_if)
);
endmodule