J
John Kimble
Guest
I'm doing a research project on this for electronics class and I'm having trouble finding information for it.
Thanks.
Thanks.
J
Jim Thompson
Guest
On Tue, 16 Mar 2004 15:11:42 GMT, "John Kimble"
<JohnKimble@JohnKimble.com> wrote:
http://www.semiconductors.philips.com/pip/74HCT85.html
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice
480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
Will you still need me, will you still feed me, when I'm sixty-four?
<JohnKimble@JohnKimble.com> wrote:
Don't you young bucks know how to Google? First hit....
http://www.semiconductors.philips.com/pip/74HCT85.html
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice
480)460-2350 | || E-mail Address at Website Fax
480)460-2142 | Brass Rat || http://www.analog-innovations.com | 1962 |
Will you still need me, will you still feed me, when I'm sixty-four?
R
R. Steve Walz
Guest
John Kimble wrote:
The logic diagram is contained within.
All you need to do to understand it is conceive of a decoder that
activates three outputs labeled "=" "<" and ">" according to whether
one 4-bit nibble input is =, <, or > the other nibble input.
A decoder is just an in-out box that takes a binary number in and
selects a specific output or specific outputs. They are assembled
by using two complementary inverters (in series) each output routed
to a column of lines, each of which represents the proposition of
an input to the chip being "1" or "0". Then inputs to a final bank
of AND gates and then a final OR gate combining them, if need be,
for each output are selectively wired to this column of proposition
lines.
See my site for examples of decoders of a few kinds:
http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS154.gif
(best example of complementary inverter chained inputs, and
vertical column of proposition lines, and N/AND outputs.
Also:
http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS138.gif
http://www.armory.com/~rstevew/Public/Tutor/Boolean/7447logic.gif
(Note that the BCD to 7-seg display contverter is also just a
decoder, a decoder is just a gate-array with a rank of inputs
and a rank of outputs. It can be expressed in Boolean equations.
Decoders can be implemented in EPROM or GALs and PLDs or in discrete
TTL gate chips, or in single MSI packages like the '138, '154, '47,
and in processors, in fact microcode in uC's and uP's is often
implemented with decoders and latching and counting logic.
-Steve
--
-Steve Walz rstevew@armory.com ftp://ftp.armory.com/pub/user/rstevew
Electronics Site!! 1000's of Files and Dirs!! With Schematics Galore!!
http://www.armory.com/~rstevew or http://www.armory.com/~rstevew/Public
http://www.semiconductors.philips.com/pip/74HCT85.html
The logic diagram is contained within.
All you need to do to understand it is conceive of a decoder that
activates three outputs labeled "=" "<" and ">" according to whether
one 4-bit nibble input is =, <, or > the other nibble input.
A decoder is just an in-out box that takes a binary number in and
selects a specific output or specific outputs. They are assembled
by using two complementary inverters (in series) each output routed
to a column of lines, each of which represents the proposition of
an input to the chip being "1" or "0". Then inputs to a final bank
of AND gates and then a final OR gate combining them, if need be,
for each output are selectively wired to this column of proposition
lines.
See my site for examples of decoders of a few kinds:
http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS154.gif
(best example of complementary inverter chained inputs, and
vertical column of proposition lines, and N/AND outputs.
Also:
http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS138.gif
http://www.armory.com/~rstevew/Public/Tutor/Boolean/7447logic.gif
(Note that the BCD to 7-seg display contverter is also just a
decoder, a decoder is just a gate-array with a rank of inputs
and a rank of outputs. It can be expressed in Boolean equations.
Decoders can be implemented in EPROM or GALs and PLDs or in discrete
TTL gate chips, or in single MSI packages like the '138, '154, '47,
and in processors, in fact microcode in uC's and uP's is often
implemented with decoders and latching and counting logic.
-Steve
--
-Steve Walz rstevew@armory.com ftp://ftp.armory.com/pub/user/rstevew
Electronics Site!! 1000's of Files and Dirs!! With Schematics Galore!!
http://www.armory.com/~rstevew or http://www.armory.com/~rstevew/Public